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參數(shù)資料
| 型號： | A8237 |
| 廠商： | Altera Corporation |
| 英文描述： | PROGRAMMABLE DMA CONTROLLER |
| 中文描述： | 可編程DMA控制器 |
| 文件頁數(shù)： | 20/22頁 |
| 文件大小： | 269K |
| 代理商： | A8237 |
24
Altera Corporation
a8237 Programmable DMA Controller Data Sheet
Figure 3. a8237 Timing Waveforms (Part 3 of 3)
Variations &
Clarifications
The following list provides clarifications on Altera’s implementation of
the
a8237
and the functionality of the Intel 8237A and Harris 82C27A
devices. Altera believes that the
a8237
provides consistent functionality
to that of the Intel and Harris devices. These interpretations have been
implemented in the Altera
a8237
MegaCore function and are believed to
be consistent with the implementation of the Intel and Harris devices.
I
The
neopin
is asserted for at least one clock cycle terminates a DMA
cycle at the end of the current transfer. The
neopin
output is asserted
at the normal conclusion of a DMA cycle, but not asserted when the
DMA cycle is aborted by a
neopin
.
The
reset
input or the master clear command clears the temporary
data register used in memory-to-memory transfers, including the
temporary address and word count registers.
The
a8237
does not implement wait-state support for memory-to-
memory transfers.
I
I
The following list provides more information on the differences between
Altera’s implementation of the
a8237
and the functionality of the Intel
8237A and Harris 82C27A devices.
I
In the
a8237
function, tri-state outputs and bidirectional ports are
split into separate inputs, outputs, and enables as necessary.
Host Processor Write Timing
ncs
niowin
ain[3..0]
dbin[7..0]
Address Valid
Address Valid
Host Processor Read Timing
ncs
niorin
ain[3..0]
dbout[7..0]
Address Valid
Data Valid
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