參數(shù)資料
型號(hào)： A8237
廠商： Altera Corporation
英文描述： PROGRAMMABLE DMA CONTROLLER
中文描述： 可編程DMA控制器
文件頁(yè)數(shù)： 15/22頁(yè)
文件大小： 269K
代理商： A8237
Altera Corporation
19
a8237 Programmable DMA Controller Data Sheet
For memory-to-memory transfers, eight states are executed: four states to
read a memory location and store the data value in the temporary register,
and another four to write the data value to a new memory location. The
equivalent of a S1 state is always executed for both memory accesses.
To compensate for slower memory or peripherals, additional wait states
can be inserted before the write state by holding
ready
low. Returning
ready
to high halts the insertion of wait states, allowing normal operation
to continue beginning with the next cycle.
Transfer Modes
The
a8237
MegaCore function has three transfer modes: single transfer,
block transfer, and demand transfer modes.
I
In single transfer mode, only one DMA transfer is executed, and the
state machine enters the SI state to allow prioritized access by other
DMA channels.
I
In block transfer mode, the DMA transfers continue uninterrupted
until the transfer is completed or
neopin
is asserted.
I
In demand transfer mode, the DMA transfers can be interrupted by
deasserting the
dreq
input. When
dreq
is reasserted, the DMA
transfers restart from the point at which they were stopped.
Other Operations
In addition to the state machine and transfer modes, the
a8237
also
provides the following operations for controlling DMA transfers:
I
I
I
I
I
I
Auto-initialization
Verify transfer
Memory-to-memory transfer
Priority encoding
Compressed timing
Extended timing
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