參數(shù)資料
型號(hào)： A54SX72A-FG256AX79
元件分類： FPGA
英文描述： FPGA, 4024 CLBS, 72000 GATES, PBGA256
封裝： 1 MM PITCH, PLASTIC, FBGA-256
文件頁(yè)數(shù)： 4/68頁(yè)
文件大?。?/td> 498K
代理商： A54SX72A-FG256AX79
1- 8
v2.2
Boundary-Scan Testing (BST)
Automotive-grade
SX-A
devices
are
IEEE
1149.1
compliant and offer superior diagnostic and testing
capabilities by providing Boundary Scan Testing (BST)
and probing capabilities. The BST function is controlled
through the special JTAG pins (TMS, TDI, TCK, TDO, and
TRST). The functionality of the JTAG pins is defined by
two available modes: Dedicated and Flexible. TMS
cannot be employed as user I/O in either mode.
Dedicated Mode
In Dedicated mode, all JTAG pins are reserved for BST;
designers cannot use them as regular I/Os. An internal
pull-up resistor is automatically enabled on both TMS
and TDI pins, and the TMS pin will function as defined in
the IEEE 1149.1 (JTAG) specification.
To select Dedicated mode, users need to reserve the JTAG
pins in Actel’s Designer software. To reserve the JTAG
pins, users can check the "Reserve JTAG" box in "Device
Selection Wizard" (Figure 1-10 on page 1-9).
To select Dedicated mode, users need to reserve the JTAG
pins in Actel's Designer software by checking the
"Reserve JTAG" box in "Device Selection Wizard"
(Figure 1-10 on page 1-9). JTAG pins comply with LVTTL/
TTL I/O specification regardless of whether they are used
as a user I/O or a JTAG I/O. Refer to the “3.3V LVTTL
and
detailed specifications.
Table 1-2 I/O Features
Function
Description
Input Buffer Threshold Selections
3.3V PCI, LVTTL
2.5V LVCMOS2
Flexible Output Driver
3.3V PCI, LVTTL
2.5V LVCMOS2
Output Buffer
"Hot-Swap" Capability (except 3.3V PCI)
I/O on an unpowered device does not sink current
Can be used for “cold-sparing”
Selectable on an individual I/O basis
Individually selectable slew rate, high slew or low slew (The default is high slew rate).
The slew is only affected on the falling edge of an output. Rising edges of outputs are
not affected.
Power-Up
Individually selectable pull-ups and pull-downs during power-up (default is to power-up
in tristate)
Enables deterministic power-up of device
VCCA and VCCI can be powered in any order
Table 1-3 I/O Characteristics for All I/O Configurations
Hot Swappable
Slew Rate Control
Power-Up Resistor
LVTTL, LVCMOS2
Yes
Yes. Only affects falling edges of outputs
Pull-up or pull-down
3.3V PCI
No
No. High slew rate only
Pull-up or pull-down
Table 1-4 Power-up Time at which I/Os Become Active
Supply Ramp Rate
0.25V/s
0.025V/s
5V/ms
2.5V/ms
0.5V/ms
0.25V/ms
0.1V/ms
0.025V/ms
Units
s
msms
msmsms
ms
A54SX08A
10
96
0.34
0.65
2.7
5.4
12.9
50.8
A54SX16A
10
100
0.36
0.62
2.5
4.7
11.0
41.6
A54SX32A
10
100
0.46
0.74
2.8
5.2
12.1
47.2
A54SX72A
10
100
0.41
0.67
2.6
5.0
12.1
47.2
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