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參數(shù)資料
| 型號： | A54SX72A-FG256AX79 |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 4024 CLBS, 72000 GATES, PBGA256 |
| 封裝： | 1 MM PITCH, PLASTIC, FBGA-256 |
| 文件頁數(shù)： | 37/68頁 |
| 文件大?。?/td> | 498K |
| 代理商： | A54SX72A-FG256AX79 |
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v2.2
Pin Description
CLKA/B
Clock A and B
These pins are clock inputs for clock distribution
networks. Input levels are compatible with standard
LVTTL or 3.3 V PCI specifications. The clock input is
buffered prior to clocking the R-cells. If not used, these
pins must be set LOW or HIGH on the board except
A54SX72A. In A54SX72A these clocks can be configured
as user I/O.
QCLKA/B/C/D,
Quadrant Clock A, B, C, and D
I/O
These four pins are the quadrant clock inputs and are
only for A54SX72A with A, B, C and D corresponding to
bottom-left,
bottom-right,
top-left
and
top-right
quadrants, respectively. They are clock inputs for clock
distribution networks. Input levels are compatible with
standard LVTTL and 3.3 V PCI specifications. Each of these
clock inputs can drive up to a quarter of the chip, or they
can be grouped together to drive multiple quadrants.
The clock input is buffered prior to clocking the R-cells. If
not used as a clock it will behave as a regular I/O.
GND
Ground
LOW supply voltage.
HCLK
Dedicated (Hardwired)
Array Clock
This pin is the clock input for sequential modules. Input
levels
are
compatible
with
LVTTL
or
3.3 V
PCI
specifications. This input is directly wired to each R-cell
and offers clock speeds independent of the number of R-
cells being driven. If not used, this pin must be set LOW
or HIGH on the board and must not be left floating.
I/O
Input/Output
The I/O pin functions as an input, output, tristate or
bidirectional buffer. Based on certain configurations,
input and output levels are compatible with LVTTL or
3.3 V
PCI
specifications.
Unused
I/O
pins
are
automatically tristated by the Designer software.
NC
No Connection
This pin is not connected to circuitry within the device.
These pins can be driven to any voltage or can be left
floating with no effect on the operation of the device.
PRA, I/O
Probe A/B
PRB, I/O
The Probe pin is used to output data from any user-
defined design node within the device. This independent
diagnostic pin can be used in conjunction with the other
probe pin to allow real-time diagnostic output of any
signal path within the device. The Probe pin can be used
as a user-defined I/O when verification has been
completed.
The
pin’s
probe
capabilities
can
be
permanently disabled to protect programmed design
confidentiality.
TCK, I/O
Test Clock
Test clock input for diagnostic probe and device
programming. In flexible mode, TCK becomes active
when the TMS pin is set LOW (refer to Table 1-5 on
page 1-9). This pin functions as an I/O when the
boundary scan state machine reaches the “l(fā)ogic reset”
state.
TDI, I/O
Test Data Input
Serial input for boundary scan testing and diagnostic
probe. In flexible mode, TDI is active when the TMS pin is
set LOW (refer to Table 1-5 on page 1-9). This pin
functions as an I/O when the boundary scan state
machine reaches the “l(fā)ogic reset” state.
TDO, I/O
Test Data Output
Serial output for boundary scan testing. In flexible mode,
TDO is active when the TMS pin is set LOW (refer to
Table 1-5 on page 1-9). This pin functions as an I/O when
the boundary scan state machine reaches the "logic
reset" state. When Silicon Explorer II is being used, TDO
will act as an output when the "checksum" command is
run. It will return to user IO when "checksum" is
complete.
TMS
Test Mode Select
The TMS pin controls the use of the IEEE 1149.1
Boundary Scan pins (TCK, TDI, TDO, TRST). In flexible
mode when the TMS pin is set LOW, the TCK, TDI, and
TDO pins are boundary scan pins (refer to Table 1-5 on
page 1-9). Once the boundary scan pins are in test mode,
they will remain in that mode until the internal
boundary scan state machine reaches the “l(fā)ogic reset”
state. At this point, the boundary scan pins will be
released and will function as regular I/O pins. The “l(fā)ogic
reset” state is reached 5 TCK cycles after the TMS pin is
set HIGH. In dedicated test mode, TMS functions as
specified in the IEEE 1149.1 specifications.
TRST, I/O
Boundary Scan Reset Pin
Once it is configured as the JTAG Reset pin, the TRST pin
functions as an active-low input to asynchronously
initialize or reset the boundary scan circuit. The TRST pin
is equipped with an internal pull-up resistor. This pin
functions as an I/O when the “Reserve JTAG Reset Pin” is
not selected in Designer.
VCCI
Supply Voltage
Supply voltage for I/Os. See “Recommended Operating
device should be connected.
VCCA
Supply Voltage
Supply voltage for Array. See “Recommended Operating
device should be connected.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A54SX72A-FG256I | 功能描述:IC FPGA SX-A 108K 256-FBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:SX-A 產(chǎn)品培訓(xùn)模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標(biāo)準(zhǔn)包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計(jì):6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA（23x23） |
| A54SX72A-FG256M | 制造商:Microsemi Corporation 功能描述:FPGA SX-A Family 72K Gates 4024 Cells 217MHz 0.25um/0.22um (CMOS) Technology 2.5V 256-Pin FBGA 制造商:Microsemi Corporation 功能描述:FPGA SX-A 72K GATES 4024 CELLS 217MHZ 0.25UM/0.22UM 2.5V 256 - Trays 制造商:Microsemi SOC Products Group 功能描述:FPGA SX-A 72K GATES 4024 CELLS 217MHZ 0.25UM/0.22UM 2.5V 256 - Trays |
| A54SX72A-FG484 | 功能描述:IC FPGA SX-A 108K 484-FBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:SX-A 產(chǎn)品培訓(xùn)模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標(biāo)準(zhǔn)包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計(jì):6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA（23x23） |
| A54SX72A-FG484A | 功能描述:IC FPGA SX-A 108K 484-FBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:SX-A 產(chǎn)品培訓(xùn)模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標(biāo)準(zhǔn)包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計(jì):6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA（23x23） |
| A54SX72A-FG484I | 功能描述:IC FPGA SX-A 108K 484-FBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:SX-A 產(chǎn)品培訓(xùn)模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標(biāo)準(zhǔn)包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計(jì):6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA（23x23） |
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