參數(shù)資料
型號： A54SX72A-BG208
廠商： Electronic Theatre Controls, Inc.
英文描述： Hex inverters with open collector outputs 14-SOIC 0 to 70
中文描述： 的SX - A系列FPGA的
文件頁數(shù)： 26/108頁
文件大小： 720K
代理商： A54SX72A-BG208
SX-A Family FPGAs
2-6
v5.1
Table 2-10
AC Specifications (3.3 V PCI Operation)
Symbol
Parameter
Condition
Min.
Max.
Units
I
OH(AC)
Switching Current High
0 < V
OUT
≤
0.3V
CCI
1
0.3V
CCI
≤
V
OUT
< 0.9V
CCI
1
0.7V
CCI
< V
OUT
< V
CCI
1, 2
–12V
CCI
–
mA
(–17.1(V
CCI
– V
OUT
))
–
mA
–
EQ 2-3 on
page 2-7
–
(Test Point)
V
OUT
= 0.7V
CC 2
V
CCI
> V
OUT
≥
0.6V
CCI
1
0.6V
CCI
> V
OUT
> 0.1V
CCI
1
0.18V
CCI
> V
OUT
> 0
1, 2
–
–32V
CCI
mA
I
OL(AC)
Switching Current Low
16V
CCI
–
mA
(26.7V
OUT
)
–
mA
–
EQ 2-4 on
page 2-7
–
(Test Point)
V
OUT
= 0.18V
CC 2
–3 < V
IN
≤
–1
V
CCI
+ 4 > V
IN
≥
V
CCI
+ 1
0.2V
CCI
- 0.6V
CCI
load
3
0.6V
CCI
- 0.2V
CCI
load
3
–
38V
CCI
mA
I
CL
Low Clamp Current
–25 + (V
IN
+ 1)/0.015
–
mA
I
CH
High Clamp Current
25 + (V
IN
– V
CCI
– 1)/0.015
–
mA
slew
R
Output Rise Slew Rate
1
4
V/ns
slew
F
Output Fall Slew Rate
1
4
V/ns
Notes:
1. Refer to the V/I curves in
Figure 2-2 on page 2-7
. Switching current characteristics for REQ# and GNT# are permitted to be one half
of that specified here; i.e., half size output drivers may be used on these signals. This specification does not apply to CLK and RST#,
which are system outputs. “Switching Current High” specifications are not relevant to SERR#, INTA#, INTB#, INTC#, and INTD#,
which are open drain outputs.
2. Maximum current requirements must be met as drivers pull beyond the last step voltage. Equations defining these maximums (C
and D) are provided with the respective diagrams in
Figure 2-2 on page 2-7
. The equation defined maximum should be met by
design. In order to facilitate component testing, a maximum current test point is defined for each side of the output driver.
3. This parameter is to be interpreted as the cumulative edge rate across the specified range, rather than the instantaneous rate at any
point within the transition range. The specified load (diagram below) is optional; i.e., the designer may elect to meet this parameter
with an unloaded output per the latest revision of the PCI Local Bus Specification. However, adherence to both maximum and
minimum parameters is required (the maximum is no longer simply a guideline). Rise slew rate does not apply to open drain
outputs.
Output
Buffer
1/2 in. max.
10 pF
Pin
1 k/25
1 k/25
Pin
Buffer
Output
10 pF
相關(guān)PDF資料
PDF描述
A54SX72A-BG208A Hex inverters with open collector outputs 14-SOIC 0 to 70
A54SX72A-BG208B Hex inverters with open collector outputs 14-PDIP 0 to 70
A54SX72A-BG208I SX-A Family FPGAs
A54SX72A-BG208M Hex inverters with open collector outputs 14-PDIP 0 to 70
A54SX72A-CQ208 Hex inverters with open collector outputs 14-SO 0 to 70
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