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參數(shù)資料
| 型號： | A42MX16-2CQ100A |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 40MX and 42MX FPGA Families |
| 中文描述： | 40MX和42MX FPGA系列 |
| 文件頁數(shù)： | 79/120頁 |
| 文件大?。?/td> | 854K |
| 代理商： | A42MX16-2CQ100A |
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61
4958B–AUTO–11/10
Atmel ATA6285/ATA6286 [Preliminary]
3.12.3.1
Alternate Functions of Port B
The Port B pins with alternate function are shown in Table 3-22.
3.12.3.2
The Alternate Pin Configuration on Port B:
SS /PCINT7 - Port B, Bit 7
SS: Not Slave Port Select input. When the SPI is enabled as a Slave, this pin is configured as an
input regardless of the setting of DDB7. As a Slave, the SPI is activated when this pin is driven
low. When the SPI is enabled as a Master, the data direction of this pin is controlled by DDB7.
When the pin is forced to be an input, the pull-up can still be controlled by the PORTB7 bit
PCINT7, Pin Change Interrupt Source 7: The PB7 pin can serve as an external interrupt source.
PCINT6 - Port B, Bit 6
PCINT6, Pin Change Interrupt Source 6: The PB6 pin can serve as an external interrupt source.
SCK/PCINT5 - Port B, Bit 5
SCK: Master Clock output, Slave Clock input pin for SPI channel. When the SPI is enabled as a
Slave, this pin is configured as an input regardless of the setting of DDB5. When the SPI is
enabled as a Master, the data direction of this pin is controlled by DDB5. When the pin is forced
to be an input, the pull-up can still be controlled by the PORTB5 bit.
PCINT5, Pin Change Interrupt Source 5: The PB5 pin can serve as an external interrupt source.
MISO/PCINT4 - Port B, Bit 4
MISO: Master Data input, Slave Data output pin for SPI channel. When the SPI is enabled as a
Master, this pin is configured as an input regardless of the setting of DDB4. When the SPI is
enabled as a Slave, the data direction of this pin is controlled by DDB4. When the pin is forced to
be an input, the pull-up can still be controlled by the PORTB4 bit.
PCINT4, Pin Change Interrupt Source 4: The PB4 pin can serve as an external interrupt source.
Table 3-22.
Port B Pins Alternate Functions
Port Pin
Alternate Functions
PB7
SS
(SPI Bus Master Slave select)
PCINT7 (Pin Change Interrupt 7)
PB6
PCINT6 (Pin Change Interrupt 6)
PB5
SCK (SPI Bus Master output clock/Slave input clock)
PCINT5 (Pin Change Interrupt 5)
PB4
MISO (SPI Bus Master Input/Slave Output)
PCINT4 (Pin Change Interrupt 4)
PB3
MOSI (SPI Bus Master Output/Slave Input)
PCINT3 (Pin Change Interrupt 3)
PB2
T2I (Timer1, Timer2, Timer3 external input clock input)
PCINT2 (Pin Change Interrupt 2)
PB1
T3O (Timer3 output)
PCINT1 (Pin Change Interrupt 1)
PB0
T3ICP (Timer3 external input capture input)
PCINT0 (Pin Change Interrupt 0)
相關PDF資料 |
PDF描述 |
|---|---|
| A42MX24-2CQ100A | 40MX and 42MX FPGA Families |
| A42MX36-2CQ100A | 40MX and 42MX FPGA Families |
| A42MX02-2CQ100B | 40MX and 42MX FPGA Families |
| A42MX04-2CQ100B | 40MX and 42MX FPGA Families |
| A42MX09-2CQ100B | 40MX and 42MX FPGA Families |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| A42MX16-2CQ100B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-2CQ100ES | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-2CQ100I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-2CQ100M | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-2PL100 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
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