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參數(shù)資料
| 型號： | A42MX16-2CQ100A |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 40MX and 42MX FPGA Families |
| 中文描述： | 40MX和42MX FPGA系列 |
| 文件頁數(shù)： | 37/120頁 |
| 文件大?。?/td> | 854K |
| 代理商： | A42MX16-2CQ100A |
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23
4958B–AUTO–11/10
Atmel ATA6285/ATA6286 [Preliminary]
3.6.5.1
EEPROM Read/Write Access
The EEPROM Address Registers are accessible in the I/O space. The write access time for the
EEPROM is given in Table 3-1 on page 24. A self-timing function, however, lets the user soft-
ware detect when the next byte can be written. If the user code contains instructions that write
the EEPROM, some precautions must be taken. In heavily filtered power supplies, VCC is likely
to rise or fall slowly on power-up/down. This causes the device for some period of time to run at
a voltage lower than specified as minimum for the clock frequency used. See Section 3.6.5.5
“Preventing EEPROM Corruption” on page 27 for details on how to avoid problems in these
situations.
In order to prevent unintentional EEPROM writes, a specific write procedure must be followed.
Refer to Section 3.6.5.4 “The EEPROM Control Register – EECR” on page 24 for details on this.
When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is
executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next
instruction is executed.
3.6.5.2
The EEPROM Address Register - EEARH, EEARL
Bits 15..9 - Res: Reserved Bits
These bits are reserved bits in the ATA6289 and will always read as zero.
Bits 8..0 - EEAR7..0: EEPROM Address
The EEPROM Address Register - EEAR specify the EEPROM address in the 320(256) bytes
EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 319(255). The
initial value of EEAR is undefined. A proper value must be written before the EEPROM may be
accessed.
3.6.5.3
The EEPROM Data Register – EEDR
Bits 7..0 - EEDR7.0: EEPROM Data
For the EEPROM write operation, the EEDR Register contains the data to be written to the
EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the
EEDR contains the data read out from the EEPROM at the address given by EEAR.
Bit
15
14
13
12
11
10
9
8
-------
EEAR8
EEARH
EEAR[7..0]
EEARL
Bit
76543210
Read/Write
RRRRR
RR
R/W
Initial Value
XXXXXXX
X
Bit
76543210
EEDR[7..0]
EEDR
Read/Write
R/W
Initial Value
00000000
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| A42MX24-2CQ100A | 40MX and 42MX FPGA Families |
| A42MX36-2CQ100A | 40MX and 42MX FPGA Families |
| A42MX02-2CQ100B | 40MX and 42MX FPGA Families |
| A42MX04-2CQ100B | 40MX and 42MX FPGA Families |
| A42MX09-2CQ100B | 40MX and 42MX FPGA Families |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A42MX16-2CQ100B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-2CQ100ES | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-2CQ100I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-2CQ100M | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-2PL100 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
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