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參數(shù)資料
| 型號(hào)： | A42MX16-2CQ100A |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 40MX and 42MX FPGA Families |
| 中文描述： | 40MX和42MX FPGA系列 |
| 文件頁(yè)數(shù)： | 46/120頁(yè) |
| 文件大小： | 854K |
| 代理商： | A42MX16-2CQ100A |
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31
4958B–AUTO–11/10
Atmel ATA6285/ATA6286 [Preliminary]
3.7.1.3
Clock Management Status Register – CMSR
Bits 7 to 1 – Res: Reserved Bits
These bits are reserved bits at the ATA6289 and will always read as zero.
Bit 0 – ECF: External Clock input Flag Bit
This bit is set if clock monitoring circuit detect break down of the selected external input clock
(ECIN0 or ECIN1). ECF is automatically cleared when the clock monitoring Interrupt Vector is
executed. Alternatively, ECF can be cleared by writing a logic one to its bit location.
3.7.1.4
Clock Management Interrupt Mask Register – CMIMR
Bits 7 to 1 – Res: Reserved Bits
These bits are reserved bits at the ATA6289 and will always read as zero.
Bit 0 – ECIE: External Clock input Interrupt Enable Bit
Writing ECIE to one enables the clock monitoring Interrupt Vector if the I bit in SREG is set. Writ-
ing ECIE to zero disables the interrupt. The corresponding Interrupt Vector is executed when the
ECF flag, located in CMSR, is set.
Bit
76
543210
-
ECF
CMSR
Read/Write
RRRR
RRR
R/W
Initial Value
00
000000
Bit
7
6
5
432
10
-
ECIE
CMIMR
Read/Write
RR
RRR
R/W
Initial Value
0
000
00
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