Revision 13 5-9 Advance v0.5 (continued) The "I/O User Input/Output" pin description was updated to include" />
參數(shù)資料
型號(hào)： A3PE600-2FG484I
廠商： Microsemi SoC
文件頁數(shù)： 67/162頁
文件大?。?/td> 0K
描述： IC FPGA 600000 GATES 484-FBGA
標(biāo)準(zhǔn)包裝： 40
系列： ProASIC3E
RAM 位總計(jì)： 110592
輸入/輸出數(shù)： 270
門數(shù)： 600000
電源電壓： 1.425 V ~ 1.575 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 85°C
封裝/外殼： 484-BGA
供應(yīng)商設(shè)備封裝： 484-FPBGA（23x23）
ProASIC3E Flash Family FPGAs
Revision 13
5-9
Advance v0.5
(continued)
The "I/O User Input/Output" pin description was updated to include information on
what happens when the pin is unused.
2-50
The "JTAG Pins" section was updated to include information on what happens
when the pin is unused.
2-51
The "Programming" section was updated to include information concerning
serialization.
2-53
The "JTAG 1532" section was updated to include SAMPLE/PRELOAD
information.
2-54
The "DC and Switching Characteristics" chapter was updated with new
information.
Starting
on page
3-1
Table 3-6 was updated.
3-5
In Table 3-10, PAC4 was updated.
3-8
Table 3-19 was updated.
3-20
The note in Table 3-24 was updated.
3-23
All Timing Characteristics tables were updated from LVTTL to Register Delays
3-26 to
3-64
The Timing Characteristics for RAM4K9, RAM512X18, and FIFO were updated.
3-74 to
3-79
FTCKMAX was updated in Table 3-98.
3-80
Advance v0.4
(October 2005)
The "Packaging Tables" table was updated.
ii
Advance v0.3
Figure 2-11 was updated.
2-9
The "Clock Resources (VersaNets)" section was updated.
2-9
The "VersaNet Global Networks and Spine Access" section was updated.
2-9
The "PLL Macro" section was updated.
2-15
Figure 2-27 was updated.
2-28
Figure 2-20 was updated.
2-19
Table 2-5 was updated.
2-25
Table 2-6 was updated.
2-25
The "FIFO Flag Usage Considerations" section was updated.
2-27
Table 2-33 was updated.
2-51
Figure 2-24 was updated.
2-31
The "Cold-Sparing Support" section is new.
2-34
Table 2-45 was updated.
2-64
Table 2-48 was updated.
2-81
Pin descriptions in the "JTAG Pins" section were updated.
2-51
The "Pin Descriptions" section was updated.
2-50
Table 3-7 was updated.
3-6
Revision
Changes
Page
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
A3PE600-2FG896 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC3E Flash Family FPGAs
A3PE600-2FG896ES 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC3E Flash Family FPGAs
A3PE600-2FG896I 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC3E Flash Family FPGAs
A3PE600-2FG896PP 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC3E Flash Family FPGAs
A3PE600-2FGG256 功能描述:IC FPGA 600000 GATES 256-FBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:ProASIC3E 標(biāo)準(zhǔn)包裝:90 系列:ProASIC3 LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計(jì):36864 輸入/輸出數(shù):157 門數(shù):250000 電源電壓:1.425 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 125°C 封裝/外殼:256-LBGA 供應(yīng)商設(shè)備封裝:256-FPBGA（17x17）
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