2-56 Revision 13 Input Register Timing Characteristics Figure 2-27 Input Register" />
參數(shù)資料
型號: A3PE600-2FG484I
廠商: Microsemi SoC
文件頁數(shù): 131/162頁
文件大?。?/td> 0K
描述: IC FPGA 600000 GATES 484-FBGA
標準包裝: 40
系列: ProASIC3E
RAM 位總計: 110592
輸入/輸出數(shù): 270
門數(shù): 600000
電源電壓: 1.425 V ~ 1.575 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 85°C
封裝/外殼: 484-BGA
供應商設備封裝: 484-FPBGA(23x23)
ProASIC3E DC and Switching Characteristics
2-56
Revision 13
Input Register
Timing Characteristics
Figure 2-27 Input Register Timing Diagram
50%
Preset
Clear
Out_1
CLK
Data
Enable
t
ISUE
50%
t
ISUD
t
IHD
50%
t
ICLKQ
1
0
t
IHE
t
IRECPRE
t
IREMPRE
t
IRECCLR
t
IREMCLR
t
IWCLR
t
IWPRE
t
IPRE2Q
t
ICLR2Q
t
ICKMPWH tICKMPWL
50%
Table 2-86 Input Data Register Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Parameter
Description
–2
–1
Std. Units
tICLKQ
Clock-to-Q of the Input Data Register
0.24 0.27 0.32
ns
tISUD
Data Setup Time for the Input Data Register
0.26 0.30 0.35
ns
tIHD
Data Hold Time for the Input Data Register
0.00 0.00 0.00
ns
tISUE
Enable Setup Time for the Input Data Register
0.37 0.42 0.50
ns
tIHE
Enable Hold Time for the Input Data Register
0.00 0.00 0.00
ns
tICLR2Q
Asynchronous Clear-to-Q of the Input Data Register
0.45 0.52 0.61
ns
tIPRE2Q
Asynchronous Preset-to-Q of the Input Data Register
0.45 0.52 0.61
ns
tIREMCLR
Asynchronous Clear Removal Time for the Input Data Register
0.00 0.00 0.00
ns
tIRECCLR
Asynchronous Clear Recovery Time for the Input Data Register
0.22 0.25 0.30
ns
tIREMPRE
Asynchronous Preset Removal Time for the Input Data Register
0.00 0.00 0.00
ns
tIRECPRE
Asynchronous Preset Recovery Time for the Input Data Register
0.22 0.25 0.30
ns
tIWCLR
Asynchronous Clear Minimum Pulse Width for the Input Data Register
0.22 0.25 0.30
ns
tIWPRE
Asynchronous Preset Minimum Pulse Width for the Input Data Register
0.22 0.25 0.30
ns
tICKMPWH
Clock Minimum Pulse Width High for the Input Data Register
0.36 0.41 0.48
ns
tICKMPWL
Clock Minimum Pulse Width Low for the Input Data Register
0.32 0.37 0.43
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.
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