參數(shù)資料
型號(hào): A3P125-PQG208II
元件分類: FPGA
英文描述: FPGA, 3072 CLBS, 125000 GATES, 350 MHz, PQFP208
封裝: 28 X 28 MM, 3.40 MM HEIGHT, 0.50 MM PITCH, GREEN, PLASTIC, QFP-208
文件頁數(shù): 25/49頁
文件大小: 5893K
代理商: A3P125-PQG208II
ProASIC3 DC and Switching Characteristics
2- 104
v1.3
Part Number and Revision Date
Part Number 51700097-002-3
Revised August 2008
List of Changes
The following table lists critical changes that were made in the current version of the chapter.
Previous Version
Changes in Current Version (v1.3)
Page
v1.2
(June 2008)
TJ, Maximum Junction Temperature, was changed to 100° from 110 in the
"Thermal Characteristics" section and EQ 2-2. The calculated result of Maximum
Power Allowed has thus changed to 1.463 W from 1.951 W.
Values for the A3P015 device were added to Table 2-7 Quiescent Supply
Values for the A3P015 device were added to Table 2-14 Different Components
The "PLL Contribution—PPLL" section was updated to change the PPLL formula
from PAC13 + PAC14 * FCLKOUT to PDC4 + PAC13 * FCLKOUT.
Both fall and rise values were included for tDDRISUD and tDDRIHD in
The typical value for Delay Increments in Programmable Delay Blocks was
v1.1
(January 2008)
Table note references were added to Table 2-2 Recommended Operating
Conditions 1, and the order of the table notes was changed.
remove "as measured on quiet I/Os." Table note 1 was revised to remove
"estimated SSO density over cycles." Table note 2 was revised to remove "refers
only to overshoot/undershoot limits for simultaneous switching I/Os.
"
The "Power per I/O Pin" section was updated to include 3 additional tables
pertaining to input buffer power and output buffer power.
values for 3.3 V PCI/PCI-X.
updated.
v1.0
(January 2008)
column and was incorrect. It was corrected and changed to TA.
Temperature1, Maximum Operating Junction Temperature was changed from
110°C to 100°C for both commercial and industrial grades.
In the "PLL Contribution—PPLL" section, the following was deleted:
FCLKIN is the input clock frequency.
was incorrect. It previously said TJ and it was corrected and changed to TA.
相關(guān)PDF資料
PDF描述
A3P125-QN132II FPGA, 3072 CLBS, 125000 GATES, 350 MHz, BCC132
A3P125-QNG132II FPGA, 3072 CLBS, 125000 GATES, 350 MHz, BCC132
A3P125-TQ144II FPGA, 3072 CLBS, 125000 GATES, 350 MHz, PQFP144
A3P125-TQG144II FPGA, 3072 CLBS, 125000 GATES, 350 MHz, PQFP144
A3P125-VQ100II FPGA, 3072 CLBS, 125000 GATES, 350 MHz, PQFP100
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
A3P125-PQG208PS53 制造商:Microsemi SOC Products Group 功能描述:ACLA3P125-PQG208PS53 125K GATES 231MHZ 1
A3P125-QNG132 功能描述:IC FPGA 1024MAC 133I/O 132QFN RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA(現(xiàn)場(chǎng)可編程門陣列) 系列:ProASIC3 標(biāo)準(zhǔn)包裝:60 系列:XP LAB/CLB數(shù):- 邏輯元件/單元數(shù):10000 RAM 位總計(jì):221184 輸入/輸出數(shù):244 門數(shù):- 電源電壓:1.71 V ~ 3.465 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:388-BBGA 供應(yīng)商設(shè)備封裝:388-FPBGA(23x23) 其它名稱:220-1241
A3P125-QNG132I 功能描述:IC FPGA 1KB FLASH 125K 132-QFN RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA(現(xiàn)場(chǎng)可編程門陣列) 系列:ProASIC3 標(biāo)準(zhǔn)包裝:152 系列:IGLOO PLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):792 RAM 位總計(jì):- 輸入/輸出數(shù):120 門數(shù):30000 電源電壓:1.14 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 85°C 封裝/外殼:289-TFBGA,CSBGA 供應(yīng)商設(shè)備封裝:289-CSP(14x14)
A3P125-QNG132T 功能描述:IC FPGA 1KB FLASH 125K 132-QFN RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA(現(xiàn)場(chǎng)可編程門陣列) 系列:ProASIC3 標(biāo)準(zhǔn)包裝:90 系列:ProASIC3 LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計(jì):36864 輸入/輸出數(shù):157 門數(shù):250000 電源電壓:1.425 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 125°C 封裝/外殼:256-LBGA 供應(yīng)商設(shè)備封裝:256-FPBGA(17x17)
A3P125-TQ144 功能描述:IC FPGA 1KB FLASH 125K 144-TQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA(現(xiàn)場(chǎng)可編程門陣列) 系列:ProASIC3 標(biāo)準(zhǔn)包裝:152 系列:IGLOO PLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):792 RAM 位總計(jì):- 輸入/輸出數(shù):120 門數(shù):30000 電源電壓:1.14 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 85°C 封裝/外殼:289-TFBGA,CSBGA 供應(yīng)商設(shè)備封裝:289-CSP(14x14)