參數(shù)資料
型號： A3P125-QN132II
元件分類： FPGA
英文描述： FPGA, 3072 CLBS, 125000 GATES, 350 MHz, BCC132
封裝： 8 X 8 MM, 0.75 MM HEIGHT, 0.50 MM PITCH, QFN-132
文件頁數(shù)： 1/49頁
文件大?。?/td> 5893K
代理商： A3P125-QN132II
February 2009
I
2009 Actel Corporation
ProASIC3 Flash Family FPGAs
with Optional Soft ARM Support
Features and Benefits
High Capacity
15 k to 1 M System Gates
Up to 144 kbits of True Dual-Port SRAM
Up to 300 User I/Os
Reprogrammable Flash Technology
130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process
Live at Power-Up (LAPU) Level 0 Support
Single-Chip Solution
Retains Programmed Design when Powered Off
High Performance
350 MHz System Performance
3.3 V, 66 MHz 64-Bit PCI
In-System Programming (ISP) and Security
Secure ISP Using On-Chip 128-Bit Advanced Encryption
Standard (AES) Decryption (except ARM-enabled ProASIC3
devices) via JTAG (IEEE 1532–compliant)
FlashLock to Secure FPGA Contents
Low Power
Core Voltage for Low Power
Support for 1.5 V-Only Systems
Low-Impedance Flash Switches
High-Performance Routing Hierarchy
Segmented, Hierarchical Routing and Clock Structure
Advanced I/O
700 Mbps DDR, LVDS-Capable I/Os (A3P250 and above)
1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
Wide Range Power Supply Voltage Support per JESD8-B,
Allowing I/Os to Operate from 2.7 V to 3.6 V
Bank-Selectable I/O Voltages—up to 4 Banks per Chip
Single-Ended
I/O
Standards:
LVTTL,
LVCMOS
3.3 V /
2.5 V / 1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X and LVCMOS
2.5 V / 5.0 V Input
Differential I/O Standards: LVPECL, LVDS, B-LVDS, and
M-LVDS (A3P250 and above)
I/O Registers on Input, Output, and Enable Paths
Hot-Swappable and Cold Sparing I/Os
Programmable Output Slew Rate and Drive Strength
Weak Pull-Up/-Down
IEEE 1149.1 (JTAG) Boundary Scan Test
Pin-Compatible Packages across the ProASIC3 Family
Clock Conditioning Circuit (CCC) and PLL
Six CCC Blocks, One with an Integrated PLL
Configurable
Phase-Shift,
Multiply/Divide,
Delay
Capabilities and External Feedback
Wide Input Frequency Range (1.5 MHz to 350 MHz)
Embedded Memory
1 kbit of FlashROM User Nonvolatile Memory
SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM
Blocks (×1, ×2, ×4, ×9, and ×18 organizations)
True Dual-Port SRAM (except ×18)
ARM Processor Support in ProASIC3 FPGAs
M1 and M7 ProASIC3 Devices—Cortex-M1 and CoreMP7 Soft
Processor Available with or without Debug
A3P015 and A3P030 devices do not support this feature.
Supported only by A3P015 and A3P030 devices.
Table 1 ProASIC3 Product Family
ProASIC3 Devices
A3P015
A3P030
A3P060
A3P125
A3P250
A3P400
A3P600
A3P1000
ARM7 Devices 1
M7A3P1000
Cortex-M1 Devices 1
M1A3P250
M1A3P400
M1A3P600
M1A3P1000
System Gates
15 k
30 k
60 k
125 k
250 k
400 k
600 k
1 M
Typical Equivalent Macrocells
128
256
512
1,024
2,048
–
VersaTiles (D-flip-flops)
384
768
1,536
3,072
6,144
9,216
13,824
24,576
RAM kbits (1,024 bits)
–
18
36
54
108
144
4,608-Bit Blocks
––
4
8
12
24
32
FlashROM Bits
1 k
Secure (AES) ISP 2
–
Yes
Integrated PLL in CCCs
––
1
VersaNet Globals 3
6
18
I/O Banks
22
2
4
Maximum User I/Os
49
81
96
133
157
194
235
300
Package Pins
QFN
VQFP
TQFP
PQFP
FBGA
QN68
QN48, QN68,
QN132
VQ100
QN132
VQ100
TQ144
FG144
QN132
VQ100
TQ144
PQ208
FG144
QN132 5
VQ100
PQ208
FG144/256 5
PQ208
FG144/256/
484
PQ208
FG144/256/
484
PQ208
FG144/256/
484
Notes:
1. Refer to the CoreMP7 datasheet or Cortex-M1 product brief for more information.
2. AES is not available for ARM-enabled ProASIC3 devices.
3. Six chip (main) and three quadrant global networks are available for A3P060 and above.
4. For higher densities and support of additional features, refer to the ProASIC3E Flash Family FPGAs handbook.
5. The M1A3P250 device does not support this package.
v1.1
相關(guān)PDF資料
PDF描述
A3P125-QNG132II FPGA, 3072 CLBS, 125000 GATES, 350 MHz, BCC132
A3P125-TQ144II FPGA, 3072 CLBS, 125000 GATES, 350 MHz, PQFP144
A3P125-TQG144II FPGA, 3072 CLBS, 125000 GATES, 350 MHz, PQFP144
A3P125-VQ100II FPGA, 3072 CLBS, 125000 GATES, 350 MHz, PQFP100
A3P125-VQG100II FPGA, 3072 CLBS, 125000 GATES, 350 MHz, PQFP100
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
A3P125-QNG132 功能描述:IC FPGA 1024MAC 133I/O 132QFN RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:ProASIC3 標準包裝:60 系列:XP LAB/CLB數(shù):- 邏輯元件/單元數(shù):10000 RAM 位總計:221184 輸入/輸出數(shù):244 門數(shù):- 電源電壓:1.71 V ~ 3.465 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:388-BBGA 供應(yīng)商設(shè)備封裝:388-FPBGA（23x23） 其它名稱:220-1241
A3P125-QNG132I 功能描述:IC FPGA 1KB FLASH 125K 132-QFN RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:ProASIC3 標準包裝:152 系列:IGLOO PLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):792 RAM 位總計:- 輸入/輸出數(shù):120 門數(shù):30000 電源電壓:1.14 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 85°C 封裝/外殼:289-TFBGA，CSBGA 供應(yīng)商設(shè)備封裝:289-CSP（14x14）
A3P125-QNG132T 功能描述:IC FPGA 1KB FLASH 125K 132-QFN RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:ProASIC3 標準包裝:90 系列:ProASIC3 LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計:36864 輸入/輸出數(shù):157 門數(shù):250000 電源電壓:1.425 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 125°C 封裝/外殼:256-LBGA 供應(yīng)商設(shè)備封裝:256-FPBGA（17x17）
A3P125-TQ144 功能描述:IC FPGA 1KB FLASH 125K 144-TQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:ProASIC3 標準包裝:152 系列:IGLOO PLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):792 RAM 位總計:- 輸入/輸出數(shù):120 門數(shù):30000 電源電壓:1.14 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 85°C 封裝/外殼:289-TFBGA，CSBGA 供應(yīng)商設(shè)備封裝:289-CSP（14x14）
A3P125-TQ144I 功能描述:IC FPGA 1KB FLASH 125K 144-TQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:ProASIC3 標準包裝:152 系列:IGLOO PLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):792 RAM 位總計:- 輸入/輸出數(shù):120 門數(shù):30000 電源電壓:1.14 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 85°C 封裝/外殼:289-TFBGA，CSBGA 供應(yīng)商設(shè)備封裝:289-CSP（14x14）
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