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參數(shù)資料
| 型號： | A1425A-VQG100C |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 310 CLBS, 2500 GATES, 125 MHz, PQFP100 |
| 封裝： | 1 MM HEIGHT, VQFP-100 |
| 文件頁數(shù)： | 68/68頁 |
| 文件大?。?/td> | 489K |
| 代理商： | A1425A-VQG100C |
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1-183
Accelerator Series FPGAs – ACT 3 Family
I/O Pad Drivers
All pad drivers are capable of being tristate. Each buffer
connects to an associated I/O module with four signals: OE
(Output Enable), IE (Input Enable), DataOut, and DataIn.
Certain special signals used only during programming and
test also connect to the pad drivers: OUTEN (global output
enable), INEN (global input enable), and SLEW (individual
slew selection). See Figure 5.
Special I/Os
The special I/Os are of two types: temporary and permanent.
Temporary special I/Os are used during programming and
testing. They function as normal I/Os when the MODE pin is
inactive. Permanent special I/Os are user programmed as
either normal I/Os or special I/Os. Their function does not
change once the device has been programmed. The
permanent special I/Os consist of the array clock input
buffers (CLKA and CLKB), the hard-wired array clock input
buffer (HCLK), the hard-wired I/O clock input buffer
(IOCLK), and the hard-wired I/O register preset/clear input
buffer (IOPCL). Their function is determined by the I/O
macros selected.
Clock Networks
The ACT 3 architecture contains four clock networks: two
high-performance dedicated clock networks and two general
purpose routed networks. The high-performance networks
function up to 200 MHz, while the general purpose routed
networks function up to 150 MHz.
Dedicated Clocks
Dedicated clock networks support high performance by
providing
sub-nanosecond
skew
and
guaranteed
performance.
Dedicated
clock
networks
contain
no
programming elements in the path from the I/O Pad Driver to
the input of S-modules or I/O modules. There are two
dedicated clock networks: one for the array registers (HCLK),
and one for the I/O registers (IOCLK). The clock networks
are accessed by special I/Os.
Figure 4 Functional Diagram for I/O Module
D
DATAOUT
D
Q
CLR/PRE
DATAIN
IOCLK
IOPCL
Y
D
Q
CLR/PRE
ODE
MUX
1
0
MUX
1
0
MUX
0
1
MUX
3
0
1
2
S1
S0
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相關代理商/技術參數(shù) |
參數(shù)描述 |
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| A1425A-VQG100I | 功能描述:IC FPGA 2500 GATES 100-VQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:ACT™ 3 產品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標準包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計:3200 輸入/輸出數(shù):80 門數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應商設備封裝:120-CPGA（34.55x34.55） |
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| A1425LK-T | 功能描述:IC SENSOR HALL EFFECT AC 4-SIP RoHS:是 類別:傳感器，轉換器 >> 磁性 - 霍爾效應，數(shù)字式開關，線性，羅盤 (IC) 系列:- 標準包裝:1 系列:- 傳感范圍:20mT ~ 80mT 類型:旋轉 電源電壓:4.5 V ~ 5.5 V 電流 - 電源:15mA 電流 - 輸出（最大）:- 輸出類型:數(shù)字式，PWM，8.5 位串行 特點:可編程 工作溫度:-40°C ~ 150°C 封裝/外殼:20-SSOP（0.209"，5.30mm 寬） 供應商設備封裝:20-SSOP 包裝:Digi-Reel® 其它名稱:AS5132-HSST-500DKR |
| A1425-PQ160C | 制造商:Microsemi SOC Products Group 功能描述: |
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