參數(shù)資料
型號(hào): A1425A-VQG100C
元件分類: FPGA
英文描述: FPGA, 310 CLBS, 2500 GATES, 125 MHz, PQFP100
封裝: 1 MM HEIGHT, VQFP-100
文件頁數(shù): 29/68頁
文件大?。?/td> 489K
代理商: A1425A-VQG100C
1-209
Accelerator Series FPGAs – ACT 3 Family
A1440A, A14V40A Timing Characteristics (continued)
(Worst-Case Commercial Conditions)
Note:
1.
Delays based on 35pF loading.
I/O Module – TTL Output Timing1
‘–3’ Speed
‘–2’ Speed
‘–1’ Speed
‘Std’ Speed
3.3V Speed
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max. Units
tDHS
Data to Pad, High Slew
5.0
5.6
6.4
7.5
9.8
ns
tDLS
Data to Pad, Low Slew
8.0
9.0
10.2
12.0
15.6
ns
tENZHS
Enable to Pad, Z to H/L,
Hi Slew
4.0
4.5
5.1
6.0
7.8
ns
tENZLS
Enable to Pad, Z to H/L,
Lo Slew
7.4
8.3
9.4
11.0
14.3
ns
tENHSZ
Enable to Pad, H/L to Z,
Hi Slew
7.4
8.3
9.4
11.0
14.3
ns
tENLSZ
Enable to Pad, H/L to Z,
Lo Slew
7.4
8.3
9.4
11.0
14.3
ns
tCKHS
IOCLK Pad to Pad H/L,
Hi Slew
8.5
9.5
11.0
14.3
ns
tCKLS
IOCLK Pad to Pad H/L,
Lo Slew
11.3
13.5
15.0
19.5
ns
dTLHHS
Delta Low to High, Hi Slew
0.02
0.03
0.04
ns/pF
dTLHLS
Delta Low to High, Lo Slew
0.05
0.06
0.07
0.09
ns/pF
dTHLHS
Delta High to Low, Hi Slew
0.04
0.05
0.07
ns/pF
dTHLLS
Delta High to Low, Lo Slew
0.05
0.06
0.07
0.09
ns/pF
I/O Module – CMOS Output Timing1
tDHS
Data to Pad, High Slew
6.2
7.0
7.9
9.3
12.1
ns
tDLS
Data to Pad, Low Slew
11.7
13.1
14.9
17.5
22.8
ns
tENZHS
Enable to Pad, Z to H/L,
Hi Slew
5.2
5.9
6.6
7.8
10.1
ns
tENZLS
Enable to Pad, Z to H/L,
Lo Slew
8.9
10.0
11.3
13.3
17.3
ns
tENHSZ
Enable to Pad, H/L to Z,
Hi Slew
7.4
8.3
9.4
11.0
14.3
ns
tENLSZ
Enable to Pad, H/L to Z,
Lo Slew
7.4
8.3
9.4
11.0
14.3
ns
tCKHS
IOCLK Pad to Pad H/L,
Hi Slew
9.0
10.1
11.8
14.3
ns
tCKLS
IOCLK Pad to Pad H/L,
Lo Slew
13.0
15.6
17.3
22.5
ns
dTLHHS
Delta Low to High, Hi Slew
0.04
0.05
0.06
0.08
ns/pF
dTLHLS
Delta Low to High, Lo Slew
0.07
0.08
0.09
0.11
0.14
ns/pF
dTHLHS
Delta High to Low, Hi Slew
0.03
0.04
0.05
ns/pF
dTHLLS
Delta High to Low, Lo Slew
0.04
0.05
0.07
ns/pF
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