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| 型號(hào)： | 9S12B128DGV1 |
| 英文描述： | 9S12B128 Device Guide |
| 中文描述： | 9S12B128設(shè)備指南 |
| 文件頁(yè)數(shù)： | 51/128頁(yè) |
| 文件大?。?/td> | 1823K |
| 代理商： | 9S12B128DGV1 |
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Device User Guide —9S12B128DGV1/D V01.11
51
2.2 Detailed Signal Descriptions
2.2.1 EXTAL, XTAL — Oscillator Pins
EXTALandXTALarethecrystaldriverandexternalclockpins.Onresetallthedeviceclocksarederived
from the EXTAL input frequency. XTAL is the crystal output.
PK7
ECS
ROMCTL
—
VDDX
PUCR/
PUPKE
Up
Port K I/O, Emulation Chip Select,
ROM On Enable
Port K I/O, Extended Addresses
Port M I/O
Port M I/O
Port M I/O, SCK of SPI0
Port M I/O, MOSI of SPI0
Port M I/O, SS of SPI0
Port M I/O, MISO of SPI0
Port M I/O, TX of CAN0
Port M I/O, RX of CAN0
Port P I/O, Interrupt, Channel 7 of
PWM
Port P I/O, Interrupt, PWM Channel
6
Port P I/O, Interrupt, PWM Channel 5
Port P I/O, Interrupt, PWM Channel 4
Port P I/O, Interrupt, PWM Channel 3
Port P I/O, Interrupt, PWM Channel 2
Port P I/O, Interrupt, PWM Channel 1
Port P I/O, Interrupt, PWM Channel 0
Port S I/O, SS of SPI0
Port S I/O, SCK of SPI0
Port S I/O, MOSI of SPI0
Port S I/O, MISO of SPI0
Port S I/O, TXD of SCI1
Port S I/O, RXD of SCI1
Port S I/O, TXD of SCI0
Port S I/O, RXD of SCI0
PK[5:0]
PM7
PM6
PM5
PM4
PM3
PM2
PM1
PM0
XADDR[19:14]
—
—
—
—
—
—
TXCAN0
RXCAN0
—
—
—
—
—
—
—
—
—
—
—
—
PERM/
PPSM
Disabled
SCK
MOSI
SS0
MISO0
—
—
PP7
KWP7
PWM7
—
PERP/
PPSP
PP6
KWP6
PWM6
—
PP5
PP4
PP3
PP2
PP1
PP0
PS7
PS6
PS5
PS4
PS3
PS2
PS1
PS0
KWP5
KWP4
KWP3
KWP2
KWP1
KWP0
SS0
SCK0
MOSI0
MISO0
TXD1
RXD1
TXD0
RXD0
PWM5
PWM4
PWM3
PWM2
PWM1
PWM0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PERS/
PPSS
Up
PT[7:0]
IOC[7:0]
—
—
PERT/
PPST
Disabled Port T I/O, Timer channels
NOTES
:
1. Refer to PEAR register description in HCS12 Multiplexed External Bus Interface (MEBI) Block Guide.
Pin Name
Function1
Pin Name
Function2
Pin Name
Function
3
Pin Name
Function
4
Powered
by
Internal Pull
Resistor
Description
CTRL
Reset
State
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相關(guān)代理商/技術(shù)參數(shù) |
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| 9S12DP256BDGV2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:9S12Dx256B Device Guide. also covers C derivatives and 9S12Ax256 devices |
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