參數(shù)資料
型號(hào)： 9S12B128DGV1
英文描述： 9S12B128 Device Guide
中文描述： 9S12B128設(shè)備指南
文件頁數(shù)： 50/128頁
文件大小： 1823K
代理商： 9S12B128DGV1
Device User Guide — 9S12B128DGV1/D V01.11
50
2.1.1 Signal Properties Summary
Table 2-1
summarizes the pin functionality. Signals shown in
bold
are not available in the 80 pin
package.
Table 2-1 Signal Properties
Pin Name
Function1
Pin Name
Function2
Pin Name
Function
3
Pin Name
Function
4
Powered
by
Internal Pull
Resistor
Description
CTRL
Reset
State
EXTAL
XTAL
RESET
TEST
VREGEN
XFC
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VDDPLL
None
None
Oscillator Pins
VDDR
N.A.
VDDX
VDDPLL
External Reset
Test Input
Voltage Regulator Enable Input
PLL Loop Filter
Background Debug, Tag High, Mode
Input
Port AD Inputs, Analog Inputs
AN[15:8] of ATD
Port AD Inputs, Analog Inputs
AN[7:0] of ATD
BKGD
TAGHI
MODC
—
VDDR
Always
Up
Up
PAD[15:8]
AN[15:8]
—
—
VDDA
None
None
PAD[07:00]
AN[07:00]
—
—
PA[7:0]
ADDR[15:8]/
DATA[15:8]
ADDR[7:0]/
DATA[7:0]
—
—
VDDR
PUCR/
PUPAE
PUCR/
PUPBE
PUCR/
PUPEE
While RESET pin
is low:
Down
Disabled
Port A I/O, Multiplexed Address/Data
PB[7:0]
—
—
Port B I/O, Multiplexed Address/Data
PE7
NOACC
XCLKS
—
Up
Port E I/O, Access, Clock Select
PE6
IPIPE1
MODB
—
Port E I/O, Pipe Status, Mode Input
PE5
IPIPE0
MODA
—
Port E I/O, Pipe Status, Mode Input
PE4
PE3
PE2
PE1
PE0
PH7
PH6
PH5
PH4
PH3
PH2
PH1
PH0
PJ7
PJ6
PJ[1:0]
ECLK
LSTRB
R/W
IRQ
XIRQ
KWH7
KWH6
KWH5
KWH4
KWH3
KWH2
KWH1
KWH0
KWJ7
KWJ6
KWJ[1:0]
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PUCR/
PUPEE
Mode
depende
nt
1
Port E I/O, Bus Clock Output
Port E I/O, Byte Strobe, Tag Low
Port E I/O, R/W in expanded modes
Port E Input, Maskable Interrupt
Port E Input, Non Maskable Interrupt
Port H I/O, Interrupt
Port H I/O, Interrupt
Port H I/O, Interrupt
Port H I/O, Interrupt
Port H I/O, Interrupt
Port H I/O, Interrupt
Port H I/O, Interrupt
Port H I/O, Interrupt
Port J I/O, Interrupt, SCL of IIC,
Port J I/O, Interrupt, SDA of IIC,
Port J I/O, Interrupts
TAGLO
—
—
—
—
—
—
—
—
—
—
—
SCL
SDA
—
Up
PERH/
PPSH
Disabled
VDDX
PERJ/
PPSJ
Up
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