參數(shù)資料
型號： 9LPRS501SKLF
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 微控制器/微處理器
英文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PQCC64
封裝： ROHS COMPLIANT, PLASTIC, MLF-64
文件頁數(shù)： 7/27頁
文件大?。?/td> 228K
代理商： 9LPRS501SKLF
IDTTM/ICSTM
64-pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor
1121G—05/19/11
Advance Information
ICS9LPRS501
64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR
15
FSLC
2
B0b7
FSLB
1
B0b6
FSLA
1
B0b5
CPU
MHz
SRC
MHz
PCI
MHz
REF
MHz
USB
MHz
DOT
MHz
00
0
266.66
00
1
133.33
01
0
200.00
01
1
166.66
10
0
333.33
10
1
100.00
11
0
400.00
11
1
1. FS
LA and FSLB are low-threshold inputs.Please see VIL_FS and VIH_FS specifications in
the Input/Supply/Common Output Parameters Table for correct values.
Also refer to the Test Clarification Table.
2. FS
LC is a three-level input. Please see the VIL_FS and VIH_FS
specifications in the Input/Supply/Common Output Parameters Table for correct values.
Table 1: CPU Frequency Select Table
96.00
Reserved
100.00
33.33
14.318
48.00
Pin 17
Pin 18
Spread
MHz
%
00
0
1
100.00
0.5% Down Spread
SRCCLK1 from SRC_MAIN
0
1
0
100.00
0.5% Down Spread
Only SRCCLK1 from PLL3
0
1
100.00
1% Down Spread
Only SRCCLK1 from PLL3
0
1
0
100.00
1.5% Down Spread
Only SRCCLK1 from PLL3
0
1
0
1
100.00
2% Down Spread
Only SRCCLK1 from PLL3
0
1
100.00
2.5% Down Spread
Only SRCCLK1 from PLL3
01
1
N/A
1
0
24.576
None
24.576Mhz on SE1 and SE2
1
0
1
24.576
98.304
None
24.576Mhz on SE1, 98.304Mhz on SE2
1
0
1
0
98.304
None
98.304Mhz on SE1 and SE2
1
0
1
27.000
None
27Mhz on SE1 and SE2
1
0
25.000
None
25Mhz on SE1 and SE2
11
0
1
N/A
11
1
0
N/A
11
1
N/A
Comment
PLL 3 disabled
B1b1
B1b4
B1b3
B1b2
Table 2: PLL3 Quick Configuration
Electrical Characteristics - SE1/2=25MHz
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
NOTES
Long Accuracy
ppm
see Tperiod min-max values
-100
0
100
ppm
1,2
Clock period
Tperiod
25.00MHz output nominal
39.99600
40.00400
ns
1
Absolute min/max period
Tabs
25.00MHz output nominal
39.32360
40.67640
ns
1
Rising Edge Slew Rate
tSLR
Measured from 0.8 to 2.0 V
1
1.2
2
V/ns
1
Falling Edge Slew Rate
tFLR
Measured from 2.0 to 0.8 V
1
1.3
2
V/ns
1
Duty Cycle
dt1
VT = 1.5 V
45
50.8
55
%
1
Jitter, Cycle to cycle
tjcyc-cyc
VT = 1.5 V
60
500
ps
1
Jitter, Long Term
tLTJ
VT = 1.5 V @ 10us delay
780
1000
ps
1
1Edge rate in system is measured from 0.8V to 2.0V.
2 Duty cycle, Peroid and Jitter are measured with respect to 1.5V
3 The average period over any 1us period of time
4 Using frequency counter with the measurment interval equal or greater that 0.15s, target frequencies are 14.318180 MHz, 33.333333MHz and
48.000000MHz
NOTES on SE outputs: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production).
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