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參數(shù)資料
| 型號： | 9LPRS501SKLF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PQCC64 |
| 封裝： | ROHS COMPLIANT, PLASTIC, MLF-64 |
| 文件頁數(shù)： | 23/27頁 |
| 文件大?。?/td> | 228K |
| 代理商： | 9LPRS501SKLF |
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IDTTM/ICSTM
64-pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor
1121G—05/19/11
Advance Information
ICS9LPRS501
64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR
5
TSSOP Pin Description (Continued)
Fully Integrated Regulator Connection for Desktop/Mobile Applications
PIN #
PIN NAME
TYPE
DESCRIPTION
49
VDDCPU_IO
PWR
Supply for CPU outputs. VDDCPU_IO is 1.05 to 3.3V with +/-5% tolerance
50
CPUC1_F
OUT
Complement clock of low power differenatial CPU clock pair. This clock will be free-running
during iAMT.
51
CPUT1_F
OUT
True clock of low power differential CPU clock pair. This clock will be free-running during iAMT.
52
GNDCPU
PWR
Ground Pin for CPU Outputs
53
CPUC0
OUT
Complement clock of low power differential CPU clock pair.
54
CPUT0
OUT
True clock of low power differential CPU clock pair.
55
VDDCPU
PWR
Power Supply 3.3V nominal.
56
CK_PWRGD/PD#
IN
Notifies CK505 to sample latched inputs, or iAMT entry/exit, or PWRDWN# mode
57
FSLB/TEST_MODE
IN
3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for
Vil_FS and Vih_FS values. TEST_MODE is a real time input to select between Hi-Z and REF/N
divider mode while in test mode. Refer to Test Clarification Table.
58
GNDREF
PWR
Ground pin for crystal oscillator circuit
59
X2
OUT
Crystal output, nominally 14.318MHz.
60
X1
IN
Crystal input, Nominally 14.318MHz.
61
VDDREF
PWR
Power pin for the REF outputs, 3.3V nominal.
62
REF0/FSLC/TEST_SEL
I/O
3.3V 14.318MHz reference clock/3.3V tolerant low threshold input for CPU frequency selection.
Refer to input electrical characteristics for Vil_FS and Vih_FS values/ TEST_SEL: 3-level
latched input to enable test mode. Refer to Test Clarification Table.
63
SDATA
I/O
Data pin for SMBus circuitry, 5V tolerant.
64
SCLK
IN
Clock pin of SMBus circuitry, 5V tolerant.
ICS9LPR501
ICS9LPRS501
1.05V to 3.3V
(+/-5%)
NC
PIN 48
VDDCPU_IO, Pin 49
VDDSRC_IO Pin 45,36,26
VDDPLL3_IO, Pin 20
VDD96_IO, Pin 12
SRC_IO Decoupling
Network
PLL3_IO Decoupling
Network
CPU_IO Decoupling
Network
96_IO Decoupling
Network
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 9LPRS501SKLFT | 功能描述:時鐘合成器/抖動清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| 9LPRS501YGLFT | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR |
| 9LPRS501YKLFT | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR |
| 9LPRS502HGLF | 制造商:Integrated Device Technology Inc 功能描述:IDT 9LPRS502HGLF LOGIC AND TIMING MISC - Rail/Tube 制造商:Integrated Device Technology Inc 功能描述:IDT 9LPRS502HGLF Logic and Timing Misc |
| 9LPRS502PGLF | 制造商:Integrated Device Technology Inc 功能描述:IDT 9LPRS502PGLF PHASED LOCKED LOOP (PLL) - Rail/Tube 制造商:Integrated Device Technology Inc 功能描述:IDT 9LPRS502PGLF Phased Locked Loop (PLL) |
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