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參數(shù)資料
| 型號： | 9LPRS365BKLFT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PQCC64 |
| 封裝： | PLASTIC, VQFN-64 |
| 文件頁數(shù)： | 5/28頁 |
| 文件大小： | 301K |
| 代理商： | 9LPRS365BKLFT |
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13
ICS9LPRS365
Datasheet
1218—09/01/10
Electrical Characteristics - SMBus Interface
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
UNITS
Notes
SMBus Voltage
V
DD
2.7
5.5
V
1
V
OLSMB
@ I
PULLUP
0.4
V
1
Current sinking at
V
OLSMB = 0.4 V
I
PULLUP
SMB Data Pin
4
mA
1
SCLK/SDATA
Clock/Data Rise Time
T
RI2C
(Max VIL - 0.15) to
(Min VIH + 0.15)
1000
ns
1
SCLK/SDATA
Clock/Data Fall Time
T
FI2C
(Min VIH + 0.15) to
(Max VIL - 0.15)
300
ns
1
Maximum SMBus Operating
Frequency
F
SMBUS
Block Mode
100
kHz
1
1Guaranteed by design and characterization, not 100% tested in production.
AC Electrical Characteristics - Input/Common Parameters
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
UNITS
Notes
Clk Stabilization
T
STAB
From VDD Power-Up or de-
assertion of PD# to 1st clock
1.8
ms
1
Tdrive_SRC
T
DRSRC
SRC output enable after
PCI_STOP# de-assertion
15
ns
1,2
Tdrive_PD#
T
DRPD
Differential output enable after
PD# de-assertion
300
us
1
Tdrive_CPU
T
DRSRC
CPU output enable after
CPU_STOP# de-assertion
10
ns
1,2
Tfall_PD#
T
FALL
5ns
1,2
Trise_PD#
T
RISE
5ns
1,2
1 Guaranteed by design and characterization, not 100% tested in production.
2 Optional. Only applies when PCI_STOP# and/or CPU_STOP# is present.
Fall/rise time of PD#, PCI_STOP#
and CPU_STOP# inputs
AC Electrical Characteristics - Low Power Differential Outputs
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
NOTES
Rising Edge Slew Rate
t
SLR
Differential Measurement
2.5
8
V/ns
1,2
Falling Edge Slew Rate
t
FLR
Differential Measurement
2.5
8
V/ns
1,2
Slew Rate Variation
t
SLVAR
Single-ended Measurement
20
%
1
Maximum Output Voltage
V
HIGH
Includes overshoot
1150
mV
1
Minimum Output Voltage
V
LOW
Includes undershoot
-300
mV
1
Differential Voltage Swing
V
SWING
Differential Measurement
300
mV
1
Crossing Point Voltage
V
XABS
Single-ended Measurement
300
550
mV
1,3,4
Crossing Point Variation
V
XABSVAR
Single-ended Measurement
140
mV
1,3,5
Duty Cycle
D
CYC
Differential Measurement
45
55
%
1
CPU Jitter - Cycle to Cycle
CPUJ
C2C
Differential Measurement
85
ps
1
SRC Jitter - Cycle to Cycle
SRCJ
C2C
Differential Measurement
125
ps
1
DOT Jitter - Cycle to Cycle
DOTJ
C2C
Differential Measurement
250
ps
1
CPU[1:0] Skew
CPU
SKEW10
Differential Measurement
100
ps
1
CPU[2_ITP:0] Skew
CPU
SKEW20
Differential Measurement
150
ps
1
SRC[10:0] Skew
SRC
SKEW
Differential Measurement
TBD
ps
1
*T
A = 0 - 70°C; VDD = 3.3 V +/-5%; CL =5pF, RS=22 (unless specified otherwise.)
1Guaranteed by design and characterization, not 100% tested in production.
2 Slew rate measured through Vswing centered around differential zero
3 Vxabs is defined as the voltage where CLK = CLK#
4 Only applies to the differential rising edge (CLK rising and CLK# falling)
5 Defined as the total variation of all crossing voltages of CLK rising and CLK# falling. Matching applies to rising edge rate of
CLK and falling edge of CLK#.
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