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參數(shù)資料
| 型號： | 9LPRS365BKLFT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PQCC64 |
| 封裝： | PLASTIC, VQFN-64 |
| 文件頁數(shù)： | 24/28頁 |
| 文件大?。?/td> | 301K |
| 代理商： | 9LPRS365BKLFT |
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5
ICS9LPRS365
Datasheet
1218—09/01/10
TSSOP Pin Description (Continued)
PIN #
PIN NAME
TYPE
DESCRIPTION
49
VDDCPU_IO
PWR
1.05V to 3.3V from external power supply
50
CPUC1_F
OUT
Complement clock of low power differenatial CPU clock pair. This clock will be free-running during iAMT.
51
CPUT1_F
OUT
True clock of low power differential CPU clock pair. This clock will be free-running during iAMT.
52
GNDCPU
PWR
Ground Pin for CPU Outputs
53
CPUC0
OUT
Complement clock of low power differential CPU clock pair.
54
CPUT0
OUT
True clock of low power differential CPU clock pair.
55
VDDCPU
PWR
Power Supply 3.3V nominal.
56
CK_PWRGD/PD#
IN
Notifies CK505 to sample latched inputs, or iAMT entry/exit, or PWRDWN# mode
57
FSLB/TEST_MODE
IN
3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and
Vih_FS values. TEST_MODE is a real time input to select between Hi-Z and REF/N divider mode while in
test mode. Refer to Test Clarification Table.
58
GNDREF
PWR
Ground pin for crystal oscillator circuit
59
X2
OUT
Crystal output, nominally 14.318MHz.
60
X1
IN
Crystal input, Nominally 14.318MHz.
61
VDDREF
PWR
Power pin for the REF outputs, 3.3V nominal.
62
REF0/FSLC/TEST_SEL
I/O
3.3V 14.318MHz reference clock/3.3V tolerant low threshold input for CPU frequency selection. Refer to
input electrical characteristics for Vil_FS and Vih_FS values/ TEST_SEL: 3-level latched input to enable
test mode. Refer to Test Clarification Table.
63
SDATA
I/O
Data pin for SMBus circuitry, 5V tolerant.
64
SCLK
IN
Clock pin of SMBus circuitry, 5V tolerant.
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