參數(shù)資料
型號： 9LPRS365BKLFT
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 微控制器/微處理器
英文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PQCC64
封裝： PLASTIC, VQFN-64
文件頁數(shù)： 23/28頁
文件大小： 301K
代理商： 9LPRS365BKLFT
4
ICS9LPRS365
Datasheet
1218—09/01/10
TSSOP Pin Description (Continued)
PIN #
PIN NAME
TYPE
DESCRIPTION
33
SRCT11/CR#_H
I/O
SRC11 true or Clock Request control H for SRC10 pair
The power-up default is SRC11, but this pin may also be used as a Clock Request control of SRC10 via
SMBus. Before configuring this pin as a Clock Request Pin, the SRC11 output pair must first be disabled in
byte 3, bit 7 of SMBus configuration space After the SRC11 output is disabled (high-Z), the pin can then be
set to serve as a Clock Request for SRC10 pair using byte 6, bit 4 of SMBus configuration space
Byte 6, bit 4
0 = SRC11 enabled (default)
1= CR#_H controls SRC10.
34
SRCT10
OUT
True clock of differential SRC clock pair.
35
SRCC10
OUT
Complement clock of differential SRC clock pair.
36
VDDSRC_IO
PWR
1.05V to 3.3V from external power supply
37
CPU_STOP#
IN
Stops all CPU Clocks, except those set to be free running clocks. In AMT mode 3 bits are shifted in from
the ICH to set the FSC, FSB, FSA values
38
PCI_STOP#
IN
Stops all PCI Clocks, except those set to be free running clocks. In AMT mode 3 bits are shifted in from
the ICH to set the FSC, FSB, FSA values
39
VDDSRC
PWR
VDD pin for SRC Pre-drivers, 3.3V nominal
40
SRCC6
OUT
Complement clock of low power differential SRC clock pair.
41
SRCT6
OUT
True clock of low power differential SRC clock pair.
42
GNDSRC
PWR
Ground for SRC clocks
43
SRCC7/CR#_E
I/O
SRC7 complement or Clock Request control E for SRC6 pair
The power-up default is SRC7#, but this pin may also be used as a Clock Request control of SRC6 via
SMBus. Before configuring this pin as a Clock Request Pin, the SRC7 output pair must first be disabled in
byte 3, bit 3 of SMBus configuration space . After the SRC output is disabled (high-Z), the pin can then be
set to serve as a Clock Request for SRC6 pair using byte 6, bit 7 of SMBus configuration space
Byte 6, bit 7
0 = SRC7# enabled (default)
1= CR#_E controls SRC6.
44
SRCT7/CR#_F
I/O
SRC7 true or Clock Request control 8 for SRC8 pair
The power-up default is SRC7, but this pin may also be used as a Clock Request control of SRC8 via
SMBus. Before configuring this pin as a Clock Request Pin, the SRC7 output pair must first be disabled in
byte 3, bit 3 of SMBus configuration space After the SRC output is disabled (high-Z), the pin can then be
set to serve as a Clock Request for SRC8 pair using byte 6, bit 6 of SMBus configuration space
Byte 6, bit 6
0 = SRC7# enabled (default)
1 = CR#_F controls SRC8.
45
VDDSRC_IO
PWR
1.05V to 3.3V from external power supply
46
CPUC2_ITP/SRCC8
OUT
Complement clock of low power differential CPU2/Complement clock of differential SRC pair. The function
of this pin is determined by the latched input value on pin 7, PCIF5/ITP_EN on powerup. The function is as
follows:
Pin 7 latched input Value
0 = SRC8#
1 = ITP#
47
CPUT2_ITP/SRCT8
OUT
True clock of low power differential CPU2/True clock of differential SRC pair. The function of this pin is
determined by the latched input value on pin 7, PCIF5/ITP_EN on powerup. The function is as follows:
Pin 7 latched input Value
0 = SRC8
1 = ITP
48
NC
N/A
No Connect
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