參數(shù)資料
型號： 9LPRS365BGLFT
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 微控制器/微處理器
英文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PDSO64
封裝： 6.10 MM, 0.50 MM PITCH, MO-153, TSSOP-64
文件頁數(shù)： 9/28頁
文件大?。?/td> 301K
代理商： 9LPRS365BGLFT
17
ICS9LPRS365
Datasheet
1218—09/01/10
FSLC
2
B0b7
FSLB
1
B0b6
FSLA
1
B0b5
CPU
MHz
SRC
MHz
PCI
MHz
REF
MHz
USB
MHz
DOT
MHz
000
266.66
001
133.33
010
200.00
011
166.66
100
333.33
101
100.00
110
400.00
111
1. FS
LA and FSLB are low-threshold inputs.Please see VIL_FS and VIH_FS specifications in
the Input/Supply/Common Output Parameters Table for correct values.
Also refer to the Test Clarification Table.
2. FS
LC is a three-level input. Please see the VIL_FS and VIH_FS
specifications in the Input/Supply/Common Output Parameters Table for correct values.
Table 1: CPU Frequency Select Table
96.00
100.00
33.33
14.318
48.00
Reserved
Pin17 (TSSOP)
/ Pin24 (MLF)
Pin18 (TSSOP)
/ Pin25 (MLF)
Spread
MHz
%
0
000
0
1
100.00
0.5% Down Spread
SRCCLK1 from SRC_MAIN
0
1
0
100.00
0.5% Down Spread
Only SRCCLK1 from PLL3
0
1
100.00
1% Down Spread
Only SRCCLK1 from PLL3
0
1
0
100.00
1.5% Down Spread
Only SRCCLK1 from PLL3
0
1
0
1
100.00
2% Down Spread
Only SRCCLK1 from PLL3
0
1
0
100.00
2.5% Down Spread
Only SRCCLK1 from PLL3
0
011
1
N/A
0
1
0
24.576
None
24.576Mhz on SE1 and SE2
0
1
0
1
24.576
98.304
None
24.576Mhz on SE1, 98.304Mhz on SE2
0
1
0
1
0
98.304
None
98.304Mhz on SE1 and SE2
0
1
0
1
27.000
None
27Mhz on SE1 and SE2
0
1
0
25.000
None
25Mhz on SE1 and SE2
0
110
1
N/A
0
111
0
N/A
0
111
1
N/A
1
000
0
N/A
1
000
1
N/A
1
001
0
27MHz_nonSS
27MHz_SS
0.5% Down Spread
1
001
1
27MHz_nonSS
27MHz_SS
1% Down Spread
1
010
0
27MHz_nonSS
27MHz_SS
1.5% Down Spread
1
010
1
27MHz_nonSS
27MHz_SS
2% Down Spread
1
011
0
27MHz_nonSS
27MHz_SS
0.75% Down Spread
1
011
1
27MHz_nonSS
27MHz_SS
1.25% Down Spread
1
100
0
27MHz_nonSS
27MHz_SS
1.75% Down Spread
1
100
1
27MHz_nonSS
27MHz_SS
0.5% Center Spread
1
101
0
27MHz_nonSS
27MHz_SS
0.75% Center Spread
1
101
1
N/A
1
110
0
N/A
1
110
1
N/A
1
111
0
N/A
1
111
1
N/A
Comment
PLL 3 disabled
B1b1
B1b4
B1b3
B1b2
27_Select
Table 2: PLL3 Quick Configuration
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