參數(shù)資料
型號： 9LPRS365BGLFT
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 微控制器/微處理器
英文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PDSO64
封裝： 6.10 MM, 0.50 MM PITCH, MO-153, TSSOP-64
文件頁數(shù)： 15/28頁
文件大?。?/td> 301K
代理商： 9LPRS365BGLFT
22
ICS9LPRS365
Datasheet
1218—09/01/10
Byte 8 Device ID and Output Enable Register
Bit
Pin
Name
Description
Type
0
1
Default
7
Device_ID3
R
1
6
Device_ID2
R
1
5
Device_ID1
R
0
4
Device_ID0
R
1
3
Reserved
RW
-
0
2
Reserved
RW
-
0
1
SE1_OE
Output enable for SE1
RW
Disabled
Enabled
27_Select
power on
latch
0
SE2_OE
Output enable for SE2
RW
Disabled
Enabled
27_Select
power on
latch
Byte 9 Output Control Register
Bit
Pin
Name
Description
Type
0
1
Default
7
PCIF5 STOP EN
Allows control of PCIF5 with assertion of
PCI_STOP#
RW
Free running
Stops with
PCI_STOP#
assertion
0
6
TME_Readback
Truested Mode Enable (TME) strap status
R
normal operation
no overclocking
0
5
REF Strength
Sets the REF output drive strength
RW
1X (2Loads)
2X (3 Loads)
1
4
Test Mode Select
Allows test select, ignores REF/FSC/TestSel
RW
Outputs HI-Z
Outputs = REF/N
0
3
Test Mode Entry
Allows entry into test mode, ignores FSB/TestMode
RW
Normal operation
Test mode
0
2
IO_VOUT2
IO Output Voltage Select (Most Significant Bit)
RW
1
IO_VOUT1
IO Output Voltage Select
RW
0
IO_VOUT0
IO Output Voltage Select (Least Significant Bit)
RW
1
Byte 10 Free-Running Control Register
Bit
Pin
Name
Description
Type
0
1
Default
7
27_Selec Latch read
back
Readback of 27_Select latch
R
Dot96/ LCD_SS
/SE
SRC0/ 27MHz
27_Select
latch
6Reserved
Reserved
RW
--
1
5Reserved
Reserved
RW
--
1
4
CPU1_AMT_EN
M1 mode clk enable
RW
Disable
Enable
1
3
Reserved
RW
--
1
2
CPU 2 Stop Enable
Enables control of CPU2 with CPU_STOP#
RW
Free Running
Stoppable
1
CPU 1 Stop Enable
Enables control of CPU1 with CPU_STOP#
RW
Free Running
Stoppable
1
0
CPU 0 Stop Enable
Enables control of CPU 0 with CPU_STOP#
RW
Free Running
Stoppable
1
Byte 11 Strength Control Register
Bit
Pin
Name
Description
Type
0
1
Default
7
48MHz
RW
1x
2x
0
6
PCIF5
RW
1x
2x
0
5PCI4
RW
1x
2x
0
4PCI3
RW
1x
2x
0
3PCI2
RW
1x
2x
0
2PCI1
RW
1x
2x
0
1PCI0
RW
1x
2x
0
0
Reserved
RW
--
0
See Table 3: V_IO Selection
(Default is 0.8V)
Table of Device identifier codes, used for
differentiating between CK505 package options,
etc.
See Device ID Table
Reserved
相關(guān)PDF資料
PDF描述
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