參數(shù)資料
型號(hào)： 9LPRS365BGLFT
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類(lèi)： 微控制器/微處理器
英文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PDSO64
封裝： 6.10 MM, 0.50 MM PITCH, MO-153, TSSOP-64
文件頁(yè)數(shù)： 26/28頁(yè)
文件大?。?/td> 301K
代理商： 9LPRS365BGLFT
7
ICS9LPRS365
Datasheet
1218—09/01/10
MLF Pin Description
PIN #
PIN NAME
TYPE
DESCRIPTION
1
GNDREF
PWR
Ground pin for crystal oscillator circuit
2
X2
OUT
Crystal output, nominally 14.318MHz.
3
X1
IN
Crystal input, Nominally 14.318MHz.
4
VDDREF
PWR
Power pin for the REF outputs, 3.3V nominal.
5
REF0/FSLC/TEST_SEL
I/O
3.3V 14.318MHz reference clock/3.3V tolerant low threshold input for CPU frequency selection.
Refer to input electrical characteristics for Vil_FS and Vih_FS values/ TEST_SEL: 3-level
latched input to enable test mode. Refer to Test Clarification Table.
6
SDATA
I/O
Data pin for SMBus circuitry, 5V tolerant.
7
SCLK
IN
Clock pin of SMBus circuitry, 5V tolerant.
8
PCI0/CR#_A
I/O
3.3V PCI clock output or Clock Request control A for either SRC0 or SRC2 pair
The power-up default is PCI0 output, but this pin may also be used as a Clock Request control
of SRC pair 0 or SRC pair 2 via SMBus. Before configuring this pin as a Clock Request Pin, the
PCI output must first be disabled in byte 2, bit 0 of SMBus address space . After the PCI output
is disabled (high-Z), the pin can then be set to serve as a Clock Request pin for either SRC pair
2 or pair 0 using the CR#_A_EN bit located in byte 5 of SMBUs address space.
Byte 5, bit 7
0 = PCI0 enabled (default)
1= CR#_A enabled. Byte 5, bit 6 controls whether CR#_A controls SRC0 or SRC2 pair
Byte 5, bit 6
0 = CR#_A controls SRC0 pair (default),
1= CR#_A controls SRC2 pair
9
VDDPCI
PWR
Power supply pin for the PCI outputs, 3.3V nominal
10
PCI1/CR#_B
I/O
3.3V PCI clock output/Clock Request control B for either SRC1 or SRC4 pair
The power-up default is PCI1 output, but this pin may also be used as a Clock Request control
of SRC pair 1 or SRC pair 4 via SMBus. Before configuring this pin as a Clock Request Pin, the
PCI output must first be disabled in byte 2, bit 1 of SMBus address space . After the PCI output
is disabled (high-Z), the pin can then be set to serve as a Clock Request pin for either SRC pair
1 or pair 4 using the CR#_B_EN bit located in byte 5 of SMBUs address space.
Byte 5, bit 5
0 = PCI1 enabled (default)
1= CR#_B enabled. Byte 5, bit 6 controls whether CR#_B controls SRC1 or SRC4 pair
Byte 5, bit 4
0 = CR#_B controls SRC1 pair (default)
1= CR#_B controls SRC4 pair
11
PCI2/TME
I/O
3.3V PCI clock output / Trusted Mode Enable (TME) Latched Input. This pin is sampled on
power-up as follows
0 = Overclocking of CPU and SRC Allowed
1 = Overclocking of CPU and SRC NOT allowed
After being sampled on power-up, this pin becomes a 3.3V PCI Output
12
PCI3
OUT
3.3V PCI clock output.
13
PCI4/27_Select
I/O
3.3V PCI clock output / 27MH mode select for pin24, 25 strap. On powerup, the logic value on
this pin determines the power-up default of DOT_96/SRC0 and 27MHz/SRC1 output and the
function talbe for the pin24 and pin25.
14
PCI_F5/ITP_EN
I/O
Free running PCI clock output and ITP/SRC8 enable strap. This output is not affected by the
state of the PCI_STOP# pin. On powerup, the state of this pin determines whether pins 53 and
54 are an ITP or SRC pair.
0 =SRC8/SRC8#
1 = ITP/ITP#
15
GNDPCI
PWR
Ground for PCI clocks.
16
VDD48
PWR
Power supply for USB clock, nominal 3.3V.
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