參數(shù)資料
型號： 9LPRS365BGLFT
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 微控制器/微處理器
英文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PDSO64
封裝： 6.10 MM, 0.50 MM PITCH, MO-153, TSSOP-64
文件頁數(shù)： 27/28頁
文件大?。?/td> 301K
代理商： 9LPRS365BGLFT
8
ICS9LPRS365
Datasheet
1218—09/01/10
MLF Pin Description (Continued)
PIN #
PIN NAME
TYPE
DESCRIPTION
17
USB_48MHz/FSLA
I/O
Fixed 48MHz USB clock output. 3.3V./ 3.3V tolerant input for CPU frequency selection. Refer to
input electrical characteristics for Vil_FS and Vih_FS values.
18
GND48
PWR
Ground pin for the 48MHz outputs.
19
VDD96_IO
PWR
1.05V to 3.3V from external power supply
20
DOTT_96/SRCT0
OUT
True clock of SRC or DOT96. The power-up default function depends on 27_Select, 1= SRC0,
0=DOT96
21
DOTC_96/SRCC0
OUT
Complement clock of SRC or DOT96. The power-up default function depends on 27_Select,1=
SRC0, 0=DOT96
22
GND
PWR
Ground pin for the DOT96 clocks.
23
VDD
PWR
Power supply for SRC / SE1 and SE2 clocks, 3.3V nominal.
24
27MHz_NonSS/SRCT1/SE1
OUT
True clock of differential SRC1 clock pair / 3.3V single-ended output. 27_Select determines the
power-up default, 1=27MHz non-spread SE clock, 0 = LCD_SST 100MHz differential clock. See
table 2 for more information.
25
27MHz_SS/SRCC1/SE2
OUT
Complement clock of differential SRC1 clock pair / 3.3V single-ended output. 27_Select
determines the power-up default, 1=27MHz spread SE clock, 0 = LCD_SSC 100MHz differential
clock. See table 2 for more information.
26
GND
PWR
Ground pin for SRC / SE1 and SE2 clocks, PLL3.
27
VDDPLL3_IO
PWR
1.05V to 3.3V from external power supply
28
SRCT2/SATAT
OUT
True clock of differential SRC/SATA clock pair.
29
SRCC2/SATAC
OUT
Complement clock of differential SRC/SATA clock pair.
30
GNDSRC
PWR
Ground pin for SRC clocks.
31
SRCT3/CR#_C
I/O
True clock of differential SRC clock pair/ Clock Request control C for either SRC0 or SRC2 pair
The power-up default is SRCCLK3 output, but this pin may also be used as a Clock Request
control of SRC pair 0 or SRC pair 2 via SMBus. Before configuring this pin as a Clock Request
Pin, the SRC3 output must first be disabled in byte 4, bit 7 of SMBus address space . After the
SRC3 output is disabled, the pin can then be set to serve as a Clock Request pin for either SRC
pair 2 or pair 0 using the CR#_C_EN bit located in byte 5 of SMBUs address space.
Byte 5, bit 3
0 = SRC3 enabled (default)
1= CR#_C enabled. Byte 5, bit 2 controls whether CR#_C controls SRC0 or SRC2 pair
Byte 5, bit 2
0 = CR#_C controls SRC0 pair (default),
1= CR#_C controls SRC2 pair
32
SRCC3/CR#_D
I/O
Complementary clock of differential SRC clock pair/ Clock Request control D for either SRC1
or SRC4 pair
The power-up default is SRCCLK3 output, but this pin may also be used as a Clock Request
control of SRC pair 1 or SRC pair 4 via SMBus. Before configuring this pin as a Clock Request
Pin, the SRC3 output must first be disabled in byte 4, bit 7 of SMBus address space . After the
SRC3 output is disabled, the pin can then be set to serve as a Clock Request pin for either SRC
pair 1 or pair 4 using the CR#_D_EN bit located in byte 5 of SMBUs address space.
Byte 5, bit 1
0 = SRC3 enabled (default)
1= CR#_D enabled. Byte 5, bit 0 controls whether CR#_D controls SRC1 or SRC4 pair
Byte 5, bit 0
0 = CR#_D controls SRC1 pair (default),
1= CR#_D controls SRC4 pair
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