參數(shù)資料
型號(hào)： 9LPR501YGT
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 微控制器/微處理器
英文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PDSO64
封裝： 6.10 MM, 0.50 MM PITCH, MO-153, TSSOP-64
文件頁數(shù)： 7/22頁
文件大?。?/td> 210K
代理商： 9LPR501YGT
IDTTM/ICSTM
64-pin CK505 w/Fully Integrated Voltage Regulator
1118G—02/19/08
Advance Information
ICS9LPR501
64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR
15
Datasheet
Byte 0 FS Readback and PLL Selection Register
Bit
Pin
Name
Description
Type
0
1
Default
7
-
FSLC
CPU Freq. Sel. Bit (Most Significant)
R
See Table 1 : CPU
Frequency Select Table
Latch
6
-
FSLB
CPU Freq. Sel. Bit
R
Latch
5
-
FSLA
CPU Freq. Sel. Bit (Least Significant)
R
Latch
4-
iAMT_EN
Set via SMBus or dynamically by CK505 if
detects dynamic M1
RW
Legacy Mode
iAMT Enabled
0
3
Reserved
RW
0
2
-
SRC_Main_SEL
Select source for SRC Main
RW
SRC Main = PLL1
SRC Main = PLL3
0
1
-
SATA_SEL
Select source for SATA clock
RW
SATA = SRC_Main
SATA = PLL2
0
-
PD_Restore
1 = on Power Down de-assert return to last known
state
0 = clear all SMBus configurations as if cold
power-on and go to latches open state
This bit is ignored and treated at '1' if device is in
iAMT mode.
RW
Configuration Not Saved
Configuration Saved
1
Byte 1 DOT96 Select and PLL3 Quick Config Register
Bit
Pin
Name
Description
Type
0
1
Default
7
13/14
SRC0_SEL
Select SRC0 or DOT96
RW
SRC0
DOT96
0
6
-
PLL1_SSC_SEL
Select 0.5% down or center SSC
RW
Down spread
Center spread
0
5
PLL3_SSC_SEL
Select 0.5% down or center SSC
RW
Down spread
Center spread
0
4
PLL3_CF3
PLL3 Quick Config Bit 3
RW
0
3
PLL3_CF2
PLL3 Quick Config Bit 2
RW
0
2
PLL3_CF1
PLL3 Quick Config Bit 1
RW
0
1
PLL3_CF0
PLL3 Quick Config Bit 0
RW
1
0
PCI_SEL
RW
PCI from PLL1
PCI from SRC_MAIN
1
Byte 2 Output Enable Register
Bit
Pin
Name
Description
Type
0
1
Default
7REF_OE
Output enable for REF, if disabled output is
tri-stated
RW
Output Disabled
Output Enabled
1
6
USB_OE
Output enable for USB
RW
Output Disabled
Output Enabled
1
5
PCIF5_OE
Output enable for PCI5
RW
Output Disabled
Output Enabled
1
4
PCI4_OE
Output enable for PCI4
RW
Output Disabled
Output Enabled
1
3
PCI3_OE
Output enable for PCI3
RW
Output Disabled
Output Enabled
1
2
PCI2_OE
Output enable for PCI2
RW
Output Disabled
Output Enabled
1
PCI1_OE
Output enable for PCI1
RW
Output Disabled
Output Enabled
1
0
PCI0_OE
Output enable for PCI0
RW
Output Disabled
Output Enabled
1
Byte 3 Output Enable Register
Bit
Pin
Name
Description
Type
0
1
Default
7
SRC11_OE
Output enable for SRC11
RW
Output Disabled
Output Enabled
1
6
SRC10_OE
Output enable for SRC10
RW
Output Disabled
Output Enabled
1
5
SRC9_OE
Output enable for SRC9
RW
Output Disabled
Output Enabled
1
4
SRC8/ITP_OE
Output enable for SRC8 or ITP
RW
Output Disabled
Output Enabled
1
3
SRC7_OE
Output enable for SRC7
RW
Output Disabled
Output Enabled
1
2
SRC6_OE
Output enable for SRC6
RW
Output Disabled
Output Enabled
1
SRC5_OE
Output enable for SRC5
RW
Output Disabled
Output Enabled
1
0
SRC4_OE
Output enable for SRC4
RW
Output Disabled
Output Enabled
1
Byte 4 Output Enable and Spread Spectrum Disable Register
Bit
Pin
Name
Description
Type
0
1
Default
7
SRC3_OE
Output enable for SRC3
RW
Output Disabled
Output Enabled
1
6
SATA/SRC2_OE
Output enable for SATA/SRC2
RW
Output Disabled
Output Enabled
1
5
SRC1_OE
Output enable for SRC1
RW
Output Disabled
Output Enabled
1
4
SRC0/DOT96_OE
Output enable for SRC0/DOT96
RW
Output Disabled
Output Enabled
1
3
CPU1_OE
Output enable for CPU1
RW
Output Disabled
Output Enabled
1
2
CPU0_OE
Output enable for CPU0
RW
Output Disabled
Output Enabled
1
PLL1_SSC_ON
Enable PLL1's spread modulation
RW
Spread Disabled
Spread Enabled
1
0
PLL3_SSC_ON
Enable PLL3's spread modulation
RW
Spread Disabled
Spread Enabled
1
See Table 2: PLL3 Quick Configuration
Only applies if Byte 0, bit 2 = 0.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
9LPR502HGLF 制造商:Integrated Device Technology Inc 功能描述:PC CLOCK, TSSOP56 - Rail/Tube
9LPR502HGLFT 制造商:Integrated Device Technology Inc 功能描述:PC CLOCK, TSSOP56 - Rail/Tube
9LPR502SGLF 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 PC MAIN CLOCK RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel
9LPR502SGLFT 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 PC MAIN CLOCK RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel
9LPR502YFLFT 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:56-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR
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