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參數(shù)資料
| 型號： | 9LPR501SGLFT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PDSO64 |
| 封裝： | 6.10 MM, 0.50 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-64 |
| 文件頁數(shù)： | 9/21頁 |
| 文件大小： | 197K |
| 代理商： | 9LPR501SGLFT |
IDTTM/ICSTM
64-pin CK505 w/Fully Integrated Voltage Regulator
1118N—05/19/11
Advance Information
ICS9LPR501
64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR
17
Datasheet
Byte 16 CK505 PLL1 Spread Spectrum Control Register
Bit
Pin
Name
Description
Type
0
1
Default
7
Reserved
RW
-
0
6
SSP14
RW
-
x
5
SSP13
RW
-
X
4
SSP12
RW
-
X
3
SSP11
RW
-
X
2
SSP10
RW
-
X
1
SSP9
RW
-
X
0
SSP8
RW
-
X
Byte 17 CK505 PLL3 M/N Programming Register
Bit
Pin
Name
Description
Type
0
1
Default
7
N Div8
N Divider 8
RW
-
X
6
N Div9
N Divider 9
RW
-
X
5
M Div5
RW
-
X
4
M Div4
RW
-
X
3
M Div3
RW
-
X
2
M Div2
RW
-
X
1
M Div1
RW
-
X
0
M Div0
RW
-
X
Byte 18 CK505 PLL3 M/N Programming Register
Bit
Pin
Name
Description
Type
0
1
Default
7
N Div7
RW
-
X
6
N Div6
RW
-
X
5
N Div5
RW
-
X
4
N Div4
RW
-
X
3
N Div3
RW
-
X
2
N Div2
RW
-
X
1
N Div1
RW
-
X
0
N Div0
RW
-
X
Byte 19 CK505 PLL3 Spread Spectrum Control Register
Bit
Pin
Name
Description
Type
0
1
Default
7
SSP7
RW
-
X
6
SSP6
RW
-
X
5
SSP5
RW
-
X
4
SSP4
RW
-
X
3
SSP3
RW
-
X
2
SSP2
RW
-
X
1
SSP1
RW
-
X
0
SSP0
RW
-
X
Byte 20 CK505 PLL3 Spread Spectrum Control Register
Bit
Pin
Name
Description
Type
0
1
Default
7
Reserved
RW
-
0
6
SSP14
RW
-
X
5
SSP13
RW
-
X
4
SSP12
RW
-
X
3
SSP11
RW
-
X
2
SSP10
RW
-
X
1
SSP9
RW
-
X
0
SSP8
RW
-
X
Byte 21 M/N Enables
Bit
Pin
Name
Description
Type
0
1
Default
7
Reserved
RW
0
6
Reserved
RW
0
5
Reserved
RW
0
4
Reserved
RW
0
3
Reserved
RW
0
2
Reserved
RW
0
1
M/N Enable CPU
RW
Disable
Enable
0
M/N Enable SRC/PCI
RW
Disable
Enable
0
The decimal representation of M Div (5:0) is equal
to reference divider value. Default at power up =
latch-in or Byte 0 Rom table.
These Spread Spectrum bits will program the
spread pecentage. Contact ICS for the correct
values.
The decimal representation of N Div (9:0) is equal
to VCO divider value. Default at power up = latch-
in or Byte 0 Rom table.
These Spread Spectrum bits will program the
spread pecentage. Contact ICS for the correct
values.
These Spread Spectrum bits will program the
spread pecentage. Contact ICS for the correct
values.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| 9LPR501YGLFT | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR |
| 9LPR502HGLF | 制造商:Integrated Device Technology Inc 功能描述:PC CLOCK, TSSOP56 - Rail/Tube |
| 9LPR502HGLFT | 制造商:Integrated Device Technology Inc 功能描述:PC CLOCK, TSSOP56 - Rail/Tube |
| 9LPR502SGLF | 功能描述:時鐘合成器/抖動清除器 PC MAIN CLOCK RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| 9LPR502SGLFT | 功能描述:時鐘合成器/抖動清除器 PC MAIN CLOCK RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
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