參數(shù)資料
型號(hào)： 9LPR501SGLFT
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 微控制器/微處理器
英文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PDSO64
封裝： 6.10 MM, 0.50 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-64
文件頁數(shù)： 2/21頁
文件大?。?/td> 197K
代理商： 9LPR501SGLFT
IDTTM/ICSTM
64-pin CK505 w/Fully Integrated Voltage Regulator
1118N—05/19/11
Advance Information
ICS9LPR501
64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR
10
Datasheet
Electrical Characteristics - SE1/2=25MHz
PARAMETER
SYMBOL
CONDI TI ON S
MIN
TYP
MAX
UNITS
NOTES
Lo ng Accuracy
ppmsee Tperiod min-max values
-100
0
1 00
ppm1,2
Clock period
Tperio d
25.0 0MHz output n ominal
39.99600
40 .00400
ns
1
Absolute min/max period
T
abs
25.0 0MHz output n ominal
39.32360
40 .67640
ns
1
Rising Edge Slew Rate
tSLR
Measured from 0.8 to 2.0 V
1
1.2
2
V/ns
1
Falling Edge Sle w Rate
t
FLR
Measured from 2.0 to 0.8 V
1
1.3
2
V/ns
1
Duty C ycle
d
t1
V
T = 1.5 V
45
50.8
55
%1
Jitter, Cycle to cycle
tjcyc-cyc
VT = 1.5 V
60
500
ps
1
Jitter, Long Term
t
LT J
V
T = 1.5 V @ 10us de lay
780
1000
ps
1
Edge rate in system is measured from 0.8V to 2.0V.
2 Duty cycle, Peroid and Jitter are measured with respect to 1.5V
3 The average period over any 1us period of time
4 Using frequency counter with the measurment interval equal or greater that 0.15s, target frequencies are 14.318180 MHz, 33.333333MHz and 48.000000MHz
NOTES on SE outputs: (unless otherwise noted, guara nteed by design and characterization, not 100% tested in production).
FSLC
2
B0b7
FSLB
1
B0b6
FSLA
1
B0b5
CPU
MHz
SRC
MHz
PCI
MHz
REF
MHz
USB
MHz
DOT
MHz
0
266.66
0
1
133.33
0
1
0
200.00
0
1
166.66
1
0
333.33
1
0
1
100.00
1
0
400.00
11
1
1. FS
LA and FSLB are low-threshold inputs.Please see VIL_FS and VIH_FS specifications in
the Input/Supply/Common Output Parameters Table for correct values.
Also refer to the Test Clarification Table.
2. FS
LC is a three-level input. Please see the VIL_FS and VIH_FS
specifications in the Input/Supply/Common Output Parameters Table for correct values.
Table 1: CPU Frequency Select Table
96.00
Reserved
100.00
33.33
14.318
48.00
Pin 17
Pin 18
Spread
MHz
%
00
0
1
100.00
0.5% Down Spread
SRCCLK1 from SRC_MAIN
0
1
0
100.00
0.5% Down Spread
Only SRCCLK1 from PLL3
0
1
100.00
1% Down Spread
Only SRCCLK1 from PLL3
0
1
0
100.00
1.5% Down Spread
Only SRCCLK1 from PLL3
0
1
0
1
100.00
2% Down Spread
Only SRCCLK1 from PLL3
0
1
0
100.00
2.5% Down Spread
Only SRCCLK1 from PLL3
01
1
N/A
1
0
24.576
None
24.576Mhz on SE1 and SE2
1
0
1
24.576
98.304
None
24.576Mhz on SE1, 98.304Mhz on SE2
1
0
1
0
98.304
None
98.304Mhz on SE1 and SE2
1
0
1
27.000
None
27Mhz on SE1 and SE2
1
0
25.000
None
25Mhz on SE1 and SE2
11
0
1
N/A
11
1
0
N/A
11
1
N/A
Comment
PLL 3 disabled
B1b1
B1b4
B1b3
B1b2
Table 2: PLL3 Quick Configuration
相關(guān)PDF資料
PDF描述
9LPR501YGT SPECIALTY MICROPROCESSOR CIRCUIT, PDSO64
9LPR502YGLFT SPECIALTY MICROPROCESSOR CIRCUIT, PDSO56
9LPRS365BKLFT SPECIALTY MICROPROCESSOR CIRCUIT, PQCC64
9LPRS365BGLFT SPECIALTY MICROPROCESSOR CIRCUIT, PDSO64
9LPRS436CKLF SPECIALTY MICROPROCESSOR CIRCUIT, PQCC48
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
9LPR501YGLFT 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR
9LPR502HGLF 制造商:Integrated Device Technology Inc 功能描述:PC CLOCK, TSSOP56 - Rail/Tube
9LPR502HGLFT 制造商:Integrated Device Technology Inc 功能描述:PC CLOCK, TSSOP56 - Rail/Tube
9LPR502SGLF 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 PC MAIN CLOCK RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel
9LPR502SGLFT 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 PC MAIN CLOCK RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*