參數(shù)資料
型號(hào)： 9DB1904BKLFT
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 時(shí)鐘及定時(shí)
英文描述： 9DB SERIES, PLL BASED CLOCK DRIVER, 19 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC72
封裝： ROHS COMPLIANT, PLASTIC, MLF-72
文件頁(yè)數(shù)： 11/18頁(yè)
文件大?。?/td> 173K
代理商： 9DB1904BKLFT
IDT
19 Output Differential Buffer for PCIe Gen2 and QPI
1607C—04/19/11
9DB1904B
19 Output Differential Buffer for PCIe Gen2 and QPI
2
Pin Description
PIN #
PIN NAME
PIN TYPE
DESCRIPTION
1
IREF
OUT
This pin establishes the reference for the differential current-mode output
pairs. It requires a fixed precision resistor to ground. 475ohm is the standard
value for 100ohm differential impedance. Other impedances require different
values. See data sheet.
2
GNDA
PWR
Ground pin for the PLL core.
3
VDDA
PWR
3.3V power for the PLL core.
4HIGH_BW#
IN
3.3V input for selecting PLL Band Width
0 = High, 1= Low
5
100M_133M#_LV
IN
Low Threshold Input to select operating frequency.
See Functionality Table for Definition
6
DIF_0
OUT
0.7V differential true clock output
7
DIF_0#
OUT
0.7V differential Complementary clock output
8
DIF_1
OUT
0.7V differential true clock output
9
DIF_1#
OUT
0.7V differential Complementary clock output
10
GND
PWR
Ground pin.
11
VDD
PWR
Power supply, nominal 3.3V
12
DIF_2
OUT
0.7V differential true clock output
13
DIF_2#
OUT
0.7V differential Complementary clock output
14
DIF_3
OUT
0.7V differential true clock output
15
DIF_3#
OUT
0.7V differential Complementary clock output
16
DIF_4
OUT
0.7V differential true clock output
17
DIF_4#
OUT
0.7V differential Complementary clock output
18
OE_01234#
IN
Active low input for enabling DIF pairs 0, 1, 2, 3 and 4.
1 =disable outputs, 0 = enable outputs
19
SMBCLK
IN
Clock pin of SMBUS circuitry, 5V tolerant
20
SMBDAT
I/O
Data pin of SMBUS circuitry, 5V tolerant
21
OE5#
IN
Active low input for enabling DIF pair 5.
1 =disable outputs, 0 = enable outputs
22
DIF_5
OUT
0.7V differential true clock output
23
DIF_5#
OUT
0.7V differential Complementary clock output
24
OE6#
IN
Active low input for enabling DIF pair 6.
1 =disable outputs, 0 = enable outputs
25
DIF_6
OUT
0.7V differential true clock output
26
DIF_6#
OUT
0.7V differential Complementary clock output
27
VDD
PWR
Power supply, nominal 3.3V
28
GND
PWR
Ground pin.
29
OE7#
IN
Active low input for enabling DIF pair 7.
1 =disable outputs, 0 = enable outputs
30
DIF_7
OUT
0.7V differential true clock output
31
DIF_7#
OUT
0.7V differential Complementary clock output
32
OE8#
IN
Active low input for enabling DIF pair 8.
1 =disable outputs, 0 = enable outputs
33
DIF_8
OUT
0.7V differential true clock output
34
DIF_8#
OUT
0.7V differential Complementary clock output
35
SMB_A0
IN
SMBus address bit 0 (LSB)
36
SMB_A1
IN
SMBus address bit 1
相關(guān)PDF資料
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9DB1933AKLF 9DB SERIES, PLL BASED CLOCK DRIVER, 19 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC72
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