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參數(shù)資料
| 型號(hào)： | 97ULP877BHLF-T |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 97ULP SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA52 |
| 封裝： | LEAD FREE ANNEALED, MO-205, MO-225, BGA-52 |
| 文件頁數(shù)： | 2/14頁 |
| 文件大?。?/td> | 179K |
| 代理商： | 97ULP877BHLF-T |
10
ICS97ULP877B
0981C—04/05/05
Clock Inputs
and Outputs
80%
20%
80%
20%
tslr
tslf
VID,VOD
Figure 8. Input and Output Slew Rates
Parameter Measurement Information
tjit(hper_n)
tjit(hper_n+1)
1
fo
Y , FB_OUTC
X
Y , FB_OUTT
X
Figure 7. Half-Period Jitter
t
jit(hper)
t
jit(hper_n)
1
2xfO
=-
相關(guān)PDF資料 |
PDF描述 |
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| 97ULP877BHLF | 97ULP SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA52 |
| 97ULP877BKLF | 97ULP SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC40 |
| 97ULP877BH | 97ULP SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA52 |
| 97ULPA877AHLF-T | 97ULP SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA52 |
| 980-1 | 0 MHz - 3000 MHz, 140 deg - RF/MICROWAVE COAXIAL MECHANICAL PH SHIFTER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 97ULP877BKLF/W | 制造商:Integrated Device Technology Inc 功能描述:ZERO DLY PLL CLOCK DRVR SGL 95MHZ TO 410MHZ 40PIN VFQFPN - Tape and Reel |
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| 97ULP878AHLF | 制造商:Integrated Device Technology Inc 功能描述:97ULP878AHLF - Trays |
| 97ULP878AHLFT | 制造商:Integrated Device Technology Inc 功能描述:97ULP878AHLFT - Tape and Reel |
| 97ULP878AHT | 制造商:Integrated Device Technology Inc 功能描述:97ULP878AHT - Tape and Reel |
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