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參數(shù)資料
| 型號： | 97632-99 |
| 廠商： | PEREGRINE SEMICONDUCTOR CORP |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 300 MHz, UUC |
| 封裝： | DIE |
| 文件頁數(shù)： | 5/16頁 |
| 文件大?。?/td> | 677K |
| 代理商： | 97632-99 |
Product Specification
PE97632
Page 13 of 16
2006-2010 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0205-06
│ UltraCMOS RFIC Solutions
Figure 8. Typical Phase Noise
Phase Detector
The phase detector is triggered by rising edges
from the main Counter (fp) and the reference
counter (fc). It has two outputs, namely PD_U,
and PD_D. If the divided VCO leads the divided
reference in phase or frequency (fp leads fc),
PD_D pulses “l(fā)ow”. If the divided reference leads
the divided VCO in phase or frequency (fc leads
fp), PD_U pulses “l(fā)ow”. The width of either pulse
is directly proportional to phase offset between the
two input signals, fp and fc.
For the UP and DOWN mode, PD_U and PD_D
drive an active loop filter which controls the VCO
tune voltage. The phase detector gain is equal to
VDD / 2 п.
PD_U pulses cause an increase in VCO
frequency and PD_D pulses cause a decrease in
VCO frequency, for a positive Kv VCO.
A lock detect output, LD is also provided, via the
pin Cext. Cext is the logical “NAND” of PD_U and
PD_D waveforms, which is driven through a series
2 k
resistor. Connecting Cext to an external
shunt capacitor provides low pass filtering of this
signal. Cext also drives the input of an internal
inverting comparator with an open drain output.
Thus LD is an “AND” function of PD_U and PD_D.
A typical phase noise plot is shown below. “Trace 1” is the smoothed average, and “Trace 2” is the raw data.
Test Conditions: MASH-1-1 mode. FOUT = 1.9204 GHz, FCOMPARISON = 20 MHz, VDD = 3.3 V, Temp = 25 C,
Loop Bandwidth = 50 kHz.
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