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參數(shù)資料
| 型號： | 97632-99 |
| 廠商： | PEREGRINE SEMICONDUCTOR CORP |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 300 MHz, UUC |
| 封裝： | DIE |
| 文件頁數(shù)： | 1/16頁 |
| 文件大?。?/td> | 677K |
| 代理商： | 97632-99 |
Document No. 70-0205-06
│ www.psemi.com
2006-2010 Peregrine Semiconductor Corp. All rights reserved.
Page 1 of 16
Peregrine’s PE97632 is a high performance fractional-N PLL
capable of frequency synthesis up to 3.5 GHz. The device is
designed for superior phase noise performance while providing
an order of magnitude reduction in current consumption, when
compared with the existing commercial space PLLs.
The PE97632 features a 10/11 dual modulus prescaler,
counters, a delta sigma modulator, and a phase comparator as
shown in Figure 1. Counter values are programmable through
either a serial interface or directly hard-wired.
The PE97632 is optimized for commercial space applications.
Single Event Latch up (SEL) is physically impossible and
Single Event Upset (SEU) is better than 10-9 errors per bit / day.
Fabricated in Peregrine’s patented UltraCMOS technology,
the PE97632 offers excellent RF performance and intrinsic
radiation tolerance.
Product Specification
3.5 GHz Delta-Sigma modulated
Fractional-N Frequency Synthesizer
for Low Phase Noise Applications
Product Description
Figure 1. Block Diagram
PE97632
Features
3.5 GHz operation
÷10/11 dual modulus prescaler
Phase detector output
Serial or Direct mode access
Frequency selectivity: Comparison
frequency / 218
Low power — 40 mA at 3.3 V
Rad-Hard
Ultra-low phase noise
68-lead CQFJ
Pin compatible with the PE9763
(reference application note AN24 at
www.psemi.com)
Auxilia-
ry
20-bit
Latch
F
in
F
in
Prescaler
10/11
Main
Counter
20
Secon-
dary
20-bit
Latch
Primary
21-bit
Latch
R Counter
f
r
Phase
Detector
6
13
Sdata
PD_U
PD_D
DSM
4
18
13
+
19
20
18
K
17:0
M
8:0
A
3:0
R
5:0
Pre_en
Direct
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