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參數(shù)資料
| 型號： | 97632-99 |
| 廠商： | PEREGRINE SEMICONDUCTOR CORP |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 300 MHz, UUC |
| 封裝： | DIE |
| 文件頁數(shù)： | 16/16頁 |
| 文件大小： | 677K |
| 代理商： | 97632-99 |
Product Specification
PE97632
Page 9 of 16
2006-2010 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0205-06
│ UltraCMOS RFIC Solutions
Functional Description
The PE97632 consists of a prescaler, counters,
an 18-bit delta-sigma modulator (DSM) and a
phase detector. The dual modulus prescaler
divides the VCO frequency by either 10 or 11,
depending on the value of the modulus select.
Counters “R” and “M” divide the reference and
prescaler output, respectively, by integer values
stored in a 20-bit register.
An additional counter
(“A”) is used in the modulus select logic. The DSM
modulates the “A” counter outputs in order to
achieve the desired fractional step.
The phase-frequency detector generates up and
down frequency control signals. Data is written
into the internal registers via the three wire serial
bus. There are also various operational and test
modes and a lock detect output.
Figure 6. Functional Block Diagram
Control
Logic
Modulus
Select
10/11
Prescaler
M Counter
(9-bit)
R Counter
(6-bit)
Phase
Detector
R(5:0)
M(8:0)
A(3:0)
Sdata
Control
Pins
fr
Fin
2 k
LD
Cext
Fin
fc
fp
DSM
+
Logic
PD_U
PD_D
K(17:0)
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