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參數(shù)資料
| 型號(hào)： | 97632-99 |
| 廠商： | PEREGRINE SEMICONDUCTOR CORP |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 300 MHz, UUC |
| 封裝： | DIE |
| 文件頁數(shù)： | 2/16頁 |
| 文件大?。?/td> | 677K |
| 代理商： | 97632-99 |
Product Specification
PE97632
Document No. 70-0205-06
│ www.psemi.com
2006-2010 Peregrine Semiconductor Corp. All rights reserved.
Page 10 of 16
Main Counter Chain
Normal Operating Mode
Setting the Pre_en control bit “l(fā)ow” enables the
÷10/11 prescaler, and the part can then be operated
either in Integer-N or Fractional-N mode. The main
counter chain divides the RF input frequency (Fin) by
an integer or fractional number derived from the
values in the “M”, “A” counters and the DSM input
word K.
The Fractional-N modes use a MASH (Multi-stAge
noise SHaping) decimation structure. The
MS2_SEL pin sets the MASH mode. Setting K=0
operates the part in Integer-N mode.
MASH-1-1 mode is a 2nd order fractional dithering
using four (22) N values: N-1, N, N+1, N+2.
MASH 1-1-1 mode is a 3rd order fractional dithering
using eight (23) N values: N-3, N-2, N-1, N, N+1,
N+2, N+3, N+4.
Using the part in either MASH mode will yield a
fractional spur at a frequency equal to [K/218] x
comparison frequency. The higher order of the DSM
reduces this spur for an increase in the phase noise
and decrease in the number of valid programming
frequencies.
The DSM accumulator size is 18 bit, so the fractional
value is fixed from the ratio K/218. There is an
additional bit in the DSM that acts like an extra bit
(19th bit). This bit is enabled by setting the pin
RND_SEL “high”. Enabling this bit has the benefit
of reducing the spurious levels. However, a small
frequency offset will occur. This positive frequency
offset is calculated with the following equation.
foffset = (fr / (R + 1)) / 219
(1)
All of the following equations do not take into
account this frequency offset. If this offset is
important to a specific frequency plan, it should be
taken into account accordingly.
During normal operation, the output from the main
counter chain (fp) is related to the VCO frequency
(Fin) by the following equation:
fp = Fin / [N + K/218]
(2)
where
N = 10 x (M + 1)
A ≤ M + 1, 1 ≤ M ≤ 511
When the loop is locked, Fin is related to the
reference frequency (fr) by the following equation:
Fin = [N + K/218] x (fr / (R+1))
(3)
where
N = 10 x (M + 1)
A ≤ M + 1, 1 ≤ M ≤ 511
A consequence of the upper limit on A is that:
In Integer-N mode, Fin must be
≥ 90 x (f
r / (R+1)) to
obtain contiguous channels.
In MASH-1-1 mode, Fin must be
≥ 91 x (f
r / (R+1)) to
obtain contiguous channels.
In MASH-1-1-1 mode, Fin must be
≥ 93 x (f
r / (R+1))
to obtain contiguous channels.
The A counter can accept values as high as 15, but
in typical operation it will cycle from 0 to 9 between
increments in M. Programming the M counter with
the minimum allowed value of “1” will result in a
minimum M counter divide ratio of “2”.
Prescaler Bypass Mode (*)
Setting the frequency control register bit Pre_en
“high” allows Fin to bypass the ÷10/11 prescaler. In
this mode, the prescaler and A counter are powered
down, and the input VCO frequency is divided by the
M counter directly. The following equation relates Fin
to the reference frequency fr:
Fin = (M + 1) x (fr / (R+1))
(4)
where 1 ≤ M ≤ 511
(*) Only Integer-N mode
In frequency bypass mode, neither A counter or K
counter is used. Therefore, only Integer-N operation
is possible.
Reference Counter
The reference counter chain divides the reference
frequency fr down to the phase detector comparison
frequency fc.
The output frequency of the 6-bit R Counter is
related to the reference frequency by the following
equation:
fc = fr / (R + 1)
(5)
where 0 ≤ R ≤ 63
Note that programming R with “0” will pass the
reference frequency (fr) directly to the phase
detector.
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