參數(shù)資料
型號(hào)： 935270030157
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 1 CHANNEL(S), 3M bps, SERIAL COMM CONTROLLER, PQFP48
封裝： 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-313-2, LQFP-48
文件頁數(shù)： 51/53頁
文件大?。?/td> 704K
代理商： 935270030157
Philips Semiconductors
SC16C650A
Universal Asynchronous Receiver/Transmitter (UART)
with 32-byte FIFO and infrared (IrDA) encoder/decoder
Product data
Rev. 03 — 13 March 2003
7 of 49
9397 750 11207
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
CS0, CS1,
CS2
14, 15,
16
9, 10,
11
12, 13,
14
I
Chip select. When CS0 and CS1 are HIGH and CS2 is LOW, these
three inputs select the UART. When any of these inputs are inactive,
the UART remains inactive (refer to AS description).
CTS
40
38
36
I
Clear to send. CTS is a modem status signal. Its condition can be
checked by reading bit 4 (CTS) of the modem status register. Bit 0
(
CTS) of the modem status register indicates that CTS has changed
states since the last read from the modem status register. If the
modem status interrupt is enabled when CTS changes levels and the
auto-CTS mode is not enabled, an interrupt is generated. CTS is also
used in the auto-CTS mode to control the transmitter.
D(7:0)
2-9
43-47,
2-4
8-1
I/O
Data bus. Eight data lines with 3-State outputs provide a bi-directional
path for data, control and status information between the UART and
the CPU.
DCD
42
40
38
I
Data carrier detect. DCD is a modem status signal. Its condition can
be checked by reading bit 7 (DCD) of the modem status register. Bit 3
(
DCD) of the modem status register indicates that DCD has changed
states since the last read from the modem status register. If the
modem status interrupt is enabled when DCD changes levels, an
interrupt is generated.
DDIS
26
22
23
O
Driver disable. DDIS is active (LOW) when the CPU is not reading
data. When active, DDIS can disable an external transceiver.
DSR
41
39
37
I
Data set ready. DSR is a modem status signal. Its condition can be
checked by reading bit 5 (DSR) of the modem status register. Bit 1
(
DSR) of the modem status register indicates DSR has changed
levels since the last read from the modem status register. If the
modem status interrupt is enabled when DSR changes levels, an
interrupt is generated.
DTR
37
33
O
Data terminal ready. When active (LOW), DTR informs a modem or
data set that the UART is ready to establish communication. DTR is
placed in the active level by setting the DTR bit of the modem control
register. DTR is placed in the inactive level either as a result of a
Master Reset, during loop mode operation, or clearing the DTR bit.
INT
33
30
O
Interrupt. When active (HIGH), INT informs the CPU that the UART
has an interrupt to be serviced. Four conditions that cause an interrupt
to be issued are: a receiver error, received data that is available or
timed out (FIFO mode only), an empty transmitter holding register or
an enabled modem status interrupt. INT is reset (deactivated) either
when the interrupt is serviced or as a result of a Master Reset.
MR
39
35
I
Master Reset. When active (HIGH), MR clears most UART registers
and sets the levels of various output signals.
OUT1, OUT2 38, 35
34, 31
O
Outputs 1 and 2. These are user-designated output terminals that are
set to the active (low) level by setting respective modem control
register (MCR) bits (OUT1 and OUT2). OUT1 and OUT2 are set to
inactive the (HIGH) level as a result of Master Reset, during loop mode
operations, or by clearing bit 2 (OUT1) or bit 3 (OUT2) of the MCR.
RCLK
10
5
9
I
Receiver clock. RCLK is the 16
× baud rate clock for the receiver
section of the UART.
Table 2:
Pin description…continued
Symbol
Pin
Type
Description
PLCC44 LQFP48 DIP40
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