參數(shù)資料
型號(hào)： 935270030157
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 1 CHANNEL(S), 3M bps, SERIAL COMM CONTROLLER, PQFP48
封裝： 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-313-2, LQFP-48
文件頁(yè)數(shù)： 15/53頁(yè)
文件大?。?/td> 704K
代理商： 935270030157
Philips Semiconductors
SC16C650A
Universal Asynchronous Receiver/Transmitter (UART)
with 32-byte FIFO and infrared (IrDA) encoder/decoder
Product data
Rev. 03 — 13 March 2003
22 of 49
9397 750 11207
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
7.4 Interrupt Status Register (ISR)
The SC16C650A provides six levels of prioritized interrupts to minimize external
software interaction. The Interrupt Status Register (ISR) provides the user with six
interrupt status bits. Performing a read cycle on the ISR will provide the user with the
highest pending interrupt level to be serviced. No other interrupts are acknowledged
until the pending interrupt is serviced. Whenever the interrupt status register is read,
the interrupt status is cleared. However, it should be noted that only the current
pending interrupt is cleared by the read. A lower level interrupt may be seen after
re-reading the interrupt status bits. Table 13 “Interrupt source” shows the data values
(bits 0-5) for the six prioritized interrupt levels and the interrupt sources associated
with each of these interrupt levels.
Table 13:
Interrupt source
Priority
level
ISR[5]
ISR[4]
ISR[3]
ISR[2]
ISR[1]
ISR[0]
Source of the interrupt
1
0
00110LSR (Receiver Line Status
Register)
2
0
00100
RXRDY (Received Data
Ready)
2
0
01100
RXRDY (Receive Data
time-out)
3
0
00010
TXRDY (Transmitter
Holding Register Empty)
4
0
00000
MSR (Modem Status
Register)
5
0
10000
RXRDY (Received Xoff
signal) / Special character
6
1
00000CTS, RTS change of state
Table 14:
Interrupt Status Register bits description
Bit
Symbol
Description
7-6
ISR[7-6]
FIFOs enabled. These bits are set to a logic 0 when the FIFO is
not being used. They are set to a logic 1 when the FIFOs are
enabled.
Logic 0 or cleared = default condition.
5-4
ISR[5-4]
INT priority bits 4-3. These bits are enabled when EFR[4] is set to
a logic 1. ISR[4] indicates that matching Xoff character(s) have
been detected. ISR[5] indicates that CTS, RTS have been
generated. Note that once set to a logic 1, the ISR[4] bit will stay a
logic 1 until Xon character(s) are received.
Logic 0 or cleared = default condition.
3-1
ISR[3-1]
INT priority bits 2-0. These bits indicate the source for a pending
interrupt at interrupt priority levels 1, 2, and 3 (see Table 13).
Logic 0 or cleared = default condition.
0
ISR[0]
INT status.
Logic 0 = An interrupt is pending and the ISR contents may be
used as a pointer to the appropriate interrupt service routine.
Logic 1 = No interrupt pending (normal default condition).
相關(guān)PDF資料
PDF描述
937-SP-3044-031 4 CONTACT(S), MALE, TELECOM AND DATACOM CONNECTOR, IDC, PLUG
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