參數(shù)資料
型號(hào)： 935261475512
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 8 CHANNEL(S), 500K bps, SERIAL COMM CONTROLLER, PQCC84
封裝： PLASTIC, MO-047AF, SOT-189-3, LCC-84
文件頁(yè)數(shù)： 41/59頁(yè)
文件大?。?/td> 383K
代理商： 935261475512
Philips Semiconductors
Product specification
SC28L198
Octal UART for 3.3V and 5V supply voltage
1999 Jan 14
46
AC ELECTRICAL CHARACTERISTICS FOR COMMERCIAL AND INDUSTRIAL (3.3V)
VCC = 3.3 volts " 10%; TA = –40 to 85°C; unless otherwise specified
SYMBOL
FIGURE
PARAMETER
LIMITS
UNIT
SYMBOL
FIGURE
PARAMETER
MIN
TYP
MAX
UNIT
Reset Timing
tRES1
RESET pulse width
10
Sclk
Bus Timing
tAS
A0-A7 setup time before Sclk C3 rising edge
22
3
ns
tAH
A0-A7 hold time after Sclk C3 rising edge
30
12
ns
tCS
CEN setup time before Sclk C1 high (ASYNC)
8
3
ns
tCS
CEN setup time before Sclk C2 high (SYNC)
8
3
ns
tCH
CEN hold time after Sclk C3 high (SYNC)
25
1
Sclk
ns
tCH
CEN hold time after Sclk C4 high (ASYNC)
50
1
Sclk
ns
tSTP
Cen high befoe next C2 to stop next cycle (Sync Mode)2
30
ns
tRWS
W-Rn setup time before Sclk C2 rising edge
7
ns
tRWH
W-Rn hold time after Sclk C3 rising edge
25
1
Sclk
ns
tDD
Read cycle Data valid after Sclk C3 falling edge
20
40
ns
tDF
Read cycle data bus floating after CEN high (ASYNC)
17
30
ns
tDF
Read cycle data bus floating after C4 end (SYNC)
11
20
ns
tDS
Write cycle data setup time before Sclk C4 rising edge
25
14
ns
tDH
Write cycle data hold time after Sclk C4 rising edge
25
14
ns
tRWD
High time between CEN low (ASYNC)
15
Sclk
ns
I/O Port Pin Timing
tPS
I/O input setup time before Sclk C3 falling edge (Read IPR)
18
4
ns
tPH
I/O input hold time after Sclk C4 rising edge (Read IPR)
12
4
ns
tPD
I/O output valid from:
Write Sclk C4 rising edge (write to I/OPIOR)
50
80
ns
Interrupt Timing
tIR
IRQN from:
Internal interrupt source active bid
Software reset to IRQN inactive
Write IMR (set or clear IMR bit))3 to IRQN inactive
22
26
60
40
43
90
60
Sclk
ns
tDD
Interrupt vector valid after C3 rising edge
20
30
ns
Tx / Rx Clock Timing, External
tRX
RxC high or low time
25
8
ns
fRX4
RxC frequency (16 X)
(1 X)
0
8
1
MHz
tTX
TxC high or low time
20
7
ns
fTX4
TxC frequency (16 X)
(1 X)
0
8.0
1
MHz
Transmitter Timing
tTXD
TxD output delay from TxC low
50
90
ns
tTCS
TxC output delay from TxD output data
-15
4
15
ns
Receiver Timing
tRXS
RxD data setup time to RxC high (data)
25
14
ns
tRXH
RxD data hold time from RxC high (data)
25
14
ns
tsSTRT
RxD data low time to for receiving a valid Start Bit
17
32
bit time
Sclk Timing
tSCLKL
Min low time at Vil (0.8V)
15
10
ns
tSCLKH
Min high time at Vih (2.0V)
15
10
ns
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