- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄36334 > 935260699551 (NXP SEMICONDUCTORS) SPECIALTY CONSUMER CIRCUIT, PQFP208 PDF資料下載
參數(shù)資料
| 型號： | 935260699551 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP208 |
| 封裝： | PLASTIC, SOT-316, SQFP-208 |
| 文件頁數(shù)： | 78/148頁 |
| 文件大?。?/td> | 692K |
| 代理商： | 935260699551 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁當前第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁
1998 Apr 09
35
Philips Semiconductors
Product specication
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
SAA7146A
7.4
Register Programming Sequencer (RPS)
The RPS is used as an additional method to program or
read the registers of the SAA7146A. Its main function is
programming the registers on demand without delay via
the interrupt handler of the host system.
Because different applications of the SAA7146A can run
independently on and asynchronously to each other the
RPS is capable of running two parallel tasks. Both tasks
are completely equal to each other and each has its own
set of registers (RPS address, RPS page, HBI threshold
and RPS time out value). Each task can be separately
enabled by setting its related ERPSx bit in the Main control
register 1 (see Table 10). To allow communication
between both tasks and the CPU there are five signals
which can be set or reset from both tasks (see Table 11).
The programming of a task is defined by an instruction list
in the system main memory that consists of RPS
commands. The operation of the RPS is initiated on
command by setting the ERPS bit of the desired task in the
Main control register 1.
The processing of RPS can be controlled by a sequence
of wait commands on special events. Furthermore the
program flow can be controlled via conditional jumps
related to the communication with the host setting
semaphores or special internal interrupts.
7.4.1
RESET
During a reset the ERPSx (Enable RPS of task ‘x’) bits in
the Main control register 1 (see Table 10) of the
SAA7146A are cleared so that an RPS task has to be
explicitly started.
7.4.2
EVENT DESCRIPTION
Table 12 shows the events available during the execution
of an RPS program. The execution can for example wait
on these events to become true. In general these events
are set if a rising edge of the corresponding signal occurs
and are cleared if a falling edge of the signal occurs.
If signals are logic HIGH after the reset and no rising edge
occurs the corresponding event (available in an RPS
program execution) will not be set.
Table 12 Description of events
Note
1. If an RPS program is used to make DEBI transfer consecutive data blocks employ the following commands: LOAD
REGISTER, CLEAR SIGNAL, UPLOAD and PAUSE. Before uploading the register contents the DEBI_DONE flag
of a former transfer has to be cleared. With this, the following PAUSE command waits correctly for DEBI_DONE of
the just started DEBI block transfer.
EVENT
DESCRIPTION
IICD
IIC Done: Done ag of the I2C-bus
DEBID
DEBI Done: Done ag of DEBI; see note 1
O_FID_A; O_FID_B
Field Identication signal: for an odd eld dependent on sync detection at Port A/Port B
E_FID_A; E_FID_B
Field Identication signal: for an even eld dependent on sync-detection at Port A/Port B
HS
HPS Source: wait for processing of source line before line addressed by SLCT is done
HT
HPS Target: wait for processing of target line before line addressed by TLCT is done
VBI_A; VBI_B
Vertical Blanking Indicator at Port A/Port B: for details on this signal see Table 90
BRS_DONE
Inactive BRS data path: for details on this signal see Table 90
HPS_DONE
Inactive HPS data path between two windows: for details on this signal see Table 90
HPS_LINE_DONE
Inactive HPS data path between two lines: for details on this signal see Table 90
VTD1; VTD2; VTD3
Video Transfer Done: video DMA 1, video DMA 2 or video DMA 3 has transferred a complete
window and is ready to be reprogrammed
GPIO0
General Purpose I/O 0: this bit reects the status of the GPIO pin 0
GPIO1
General Purpose I/O 1: this bit reects the status of the GPIO pin 1
GPIO2
General Purpose I/O 2: this bit reects the status of the GPIO pin 2
GPIO3
General Purpose I/O 3: this bit reects the status of the GPIO pin 3
SIGx
General purpose signal x: for intertask and RPS to CPU communication or program ow
control. ‘x’ can take a value within the range 0 to 4
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 935260699557 | SPECIALTY CONSUMER CIRCUIT, PQFP208 |
| 935243450551 | COLOR SIGNAL ENCODER, PQFP44 |
| 935243450557 | COLOR SIGNAL ENCODER, PQFP44 |
| 935243460551 | COLOR SIGNAL ENCODER, PQFP44 |
| 935243460557 | COLOR SIGNAL ENCODER, PQFP44 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 935261069122 | 制造商:NXP Semiconductors 功能描述:IC SECURITY TRANSPONDER PLLMC |
| 935262025112 | 制造商:NXP Semiconductors 功能描述:SUB ONLY IC |
| 935262217118 | 制造商:NXP Semiconductors 功能描述:Real Time Clock Serial 8-Pin SO T/R |
| 935264217557 | 制造商:NXP Semiconductors 功能描述:SUB ONLY IC |
| 935267356112 | 制造商:NXP Semiconductors 功能描述:IC TEA1507PN |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。