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| 型號(hào)： | 935260699551 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP208 |
| 封裝： | PLASTIC, SOT-316, SQFP-208 |
| 文件頁(yè)數(shù)： | 68/148頁(yè) |
| 文件大小： | 692K |
| 代理商： | 935260699551 |
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1998 Apr 09
26
Philips Semiconductors
Product specication
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
SAA7146A
7.2.3
AUDIO DMA CONTROL
The SAA7146A provides up to four audio DMA channels,
each using a FIFO of 24 Dwords. Two channels are read
only (A1_in and A2_in) and two channels are write only
(A1_out and A2_out). Because audio represents a
continuous data stream, which is neither line nor field
dependent, the audio DMA control offers only one base
address (BaseAxx) and no pitch register. For FIFO
overflow and underflow the handling of these channels is
done in the same way as the video DMA channels
(see Section 7.2.2).
The protection violation handling differs only if the limit
register and the PV bit are programmed to zero. The audio
DMA channel does not wait for the EOF signal, like the
video ones. It does not generate interrupts. The interrupt
range specified by the limit register is defined in the same
way as described in Section 7.2.2. The audio DMA
channels try immediately to transfer data after setting the
transfer enable bits. All registers for audio DMA control,
which are the base address, the protection address and
the control bits are listed in the following Table 5, except
the input control bits (Burst, Threshold), which are listed in
Table 6.
Table 5
Audio DMA control register
OFFSET
(HEX)
NAME
BIT
TYPE
DESCRIPTION
94
BaseA1_in
31 to 0
RW
base address for audio input Channel 1; this value species a
byte address
98
ProtA1_in
31 to 2
RW
protection address for audio input Channel 1; this address
could be used to specify a upper limit for audio access in memory
space
1to0
reserved
9C
PageA1_in
31 to 12
RW
base address of the page table, see Section 7.2.4.
MEA1_in
11
RW
mapping enable; this bit enables the MMU
10 to 8
reserved
LimitA1_in
7 to 4
RW
interrupt limit; denes the size of the memory range, that
generates interrupt, if its boundaries are passed
PVA1_in
3
RW
protection violation handling
2to0
reserved
A0
BaseA1_out
31 to 0
RW
Base address for audio output Channel 1; this value species a
byte address. The lower two bits are forced to zero.
A4
ProtA1_out
31 to 2
RW
protection address for audio output Channel 1; this address
could be used to specify a upper limit for audio access in memory
space
1 and 0
reserved
A8
PageA1_out
31 to 12
RW
base address of the page table, see Section 7.2.4.
MEA1_out
11
RW
mapping enable; this bit enables the MMU
10 to 8
reserved
LimitA1_out
7 to 4
RW
interrupt limit; denes the size of the memory range, that
generates an interrupt, if its boundaries are passed
PVA1_out
3
RW
protection violation handling
2to0
reserved
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