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參數(shù)資料
| 型號(hào)： | 935249800518 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 存儲(chǔ)器 |
| 英文描述： | SPECIALTY MEMORY CIRCUIT, PDSO40 |
| 封裝： | 10.16 MM, PLASTIC, SO-40 |
| 文件頁(yè)數(shù)： | 23/30頁(yè) |
| 文件大?。?/td> | 223K |
| 代理商： | 935249800518 |
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1999 Apr 29
3
Philips Semiconductors
Product specication
2.9-Mbit eld memory
SAA4955TJ
BLOCK DIAGRAM
Fig.1 Block diagram.
handbook, full pagewidth
MGK676
SERIAL WRITE REGISTER
20-WORD (
×13)
mini cache write control
+ cache transfer
mini cache read control
OE
internal
PARALLEL WRITE REGISTER
20-WORD (
×13)
20
× (12 + 1)
MEMORY ARRAY
245760-WORD (
×12)
SAA4955TJ
MEMORY
ARBITRATION
LOGIC
WRITE ADDRESS
COUNTER
REFRESH ADDRESS
COUNTER
READ ADDRESS
COUNTER
WRITE MINI CACHE
12-WORD (
×12)
DATA INPUT AND
WRITE MASK
BUFFER (
×13)
INPUT BUFFER
(
×3)
SERIAL WRITE CONTROLLER
CLOCK
OSCILLATOR
IE
internal
OE
internal
D0
internal
20
× (12 + 1)
PARALLEL READ REGISTER
20-WORD (
×12)
20
× 12
12
27 to 38
23
OE
Q0 to Q11
RE
RSTR
SRCK
24
25
26
SERIAL READ REGISTER
20-WORD (
×12)
12
20
× 12
12
1
22
100 nF
12
14 to 3
18
17
16
15
12
+ 1
+3.3 V
IE
internal
D0
internal
cache
transfer
READ MINI CACHE
12-WORD (
×12)
DATA MUX
DATA OUTPUT
BUFFER (
×12)
INPUT BUFFER
(
×4)
12
SERIAL READ CONTROLLER
3
write
control
write
acknowledge
read
control
read
acknowledge
load write
block
address
load read
block
address
refresh clock
IE internal
D0 to D11
IE
WE
RSTW
SWCK
GNDP
2
GND
39
GNDO
40
GNDP
VDD(O)
21
VDD(P)
20
VDD(P)
19
VDD
Pins 20 and 21 (VDD(P)) should be connected to the supply voltage of the driving circuit that generates the input voltages. This could be, for instance,
5.5 V instead of 3.3 V. Pins 19 and 22 (VDD and VDD(O)) require a 3.3 V supply.
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