參數(shù)資料
型號(hào): 87C552
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: 80C51 8-bit microcontroller 8K/256 OTP, 8 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O
中文描述: 8-BIT, OTPROM, MICROCONTROLLER
文件頁數(shù): 17/24頁
文件大?。?/td> 193K
代理商: 87C552
Philips Semiconductors
Product specification
87C552
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I
2
C, PWM, capture/compare, high I/O
1998 May 01
17
V
DD
P0
EA
RST
XTAL1
XTAL2
V
SS
V
DD
V
DD
I
DD
(NC)
CLOCK SIGNAL
V
DD
P1.6
P1.7
STADC
EW
AV
SS
AV
ref–
SU00219
Figure 12. I
DD
Test Condition, Idle Mode
All other pins are disconnected
2
2. Idle Mode:
a. The following pins must be forced to V
DD
: Port 0 and EW.
b. The following pins must be forced to V
SS
: RST, STADC, AV
ss
,, AV
ref–
, and EA.
c. Ports 1.6 and 1.7 should be connected to V
DD
through resistors of sufficiently high value such that the sink current into these pins cannot
exceed the I
OL1
spec of these pins. These pins must not have logic 0 written to them prior to this measurement.
d. The following pins must be disconnected: XTAL2 and all pins not specified above.
V
DD
–0.5
0.5V
0.7V
DD
0.2V
DD
–0.1
t
CHCL
t
CLCL
t
CLCH
t
CLCX
t
CHCX
SU00220
Figure 13. Clock Signal Waveform for I
DD
Tests in Active and Idle Modes
t
CLCH
= t
CHCL
= 5ns
V
DD
P0
RST
XTAL1
XTAL2
V
SS
V
DD
V
DD
I
DD
(NC)
V
DD
P1.6
P1.7
STADC
EA
EW
AV
SS
AV
ref–
SU00221
Figure 14. I
DD
Test Condition, Power Down Mode
All other pins are disconnected. V
DD
= 2V to 5.5V
3
3. Power Down Mode:
a. The following pins must be forced to V
DD
: Port 0 and EW.
b. The following pins must be forced to V
SS
: RST, STADC, XTAL1, AV
ss
,, AV
ref–
, and EA.
c. Ports 1.6 and 1.7 should be connected to V
DD
through resistors of sufficiently high value such that the sink current into these pins cannot
exceed the I
OL1
spec of these pins. These pins must not have logic 0 written to them prior to this measurement.
d. The following pins must be disconnected: XTAL2 and all pins not specified above.
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