參數資料
型號： 87C552
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 80C51 8-bit microcontroller 8K/256 OTP, 8 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O
中文描述： 8-BIT, OTPROM, MICROCONTROLLER
文件頁數： 11/24頁
文件大?。?/td> 193K
代理商： 87C552
Philips Semiconductors
Product specification
87C552
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I
2
C, PWM, capture/compare, high I/O
1998 May 01
11
AC ELECTRICAL CHARACTERISTICS
1, 2
12MHz CLOCK
MIN
16MHz CLOCK
MIN
VARIABLE CLOCK
MIN
3.5
2t
CLCL
–40
t
CLCL
–55
t
CLCL
–35
SYMBOL
1/t
CLCL
t
LHLL
t
AVLL
t
LLAX
t
LLIV
t
LLPL
t
PLPH
t
PLIV
t
PXIX
t
PXIZ
t
AVIV
t
PLAZ
Data Memory
t
AVLL
t
RLRH
t
WLWH
t
RLDV
t
RHDX
t
RHDZ
t
LLDV
t
AVDV
t
LLWL
t
AVWL
t
QVWX
t
DW
t
WHQX
t
RLAZ
t
WHLH
External Clock
t
CHCX
t
CLCX
t
CLCH
t
CHCL
Serial Timing – Shift Register Mode
4
(Test Conditions: T
amb
= 0
°
C to +70
°
C; V
SS
= 0V; Load Capaciatnce = 80pF)
t
XLXL
6
Serial port clock cycle time
t
QVXH
6
Output data setup to clock rising edge
t
XHQX
6
Output data hold after clock rising edge
t
XHDX
6
Input data hold after clock rising edge
t
XHDV
6
Clock rising edge to input data valid
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.
3. t
CLCL
= 1/f
OSC
= one oscillator clock period.
t
CLCL
= 83.3ns at f
OSC
= 12MHz.
t
= 62.5ns at f
= 16MHz.
4. These values are characterized but not 100% production tested.
FIGURE
2
2
2
2
2
2
2
2
2
2
2
2
PARAMETER
MAX
MAX
MAX
16
UNIT
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Oscillator frequency
ALE pulse width
Address valid to ALE low
Address hold after ALE low
ALE low to valid instruction in
ALE low to PSEN low
PSEN pulse width
PSEN low to valid instruction in
Input instruction hold after PSEN
Input instruction float after PSEN
Address to valid instruction in
PSEN low to address float
127
28
48
85
8
28
234
150
4t
CLCL
–100
43
205
23
143
t
CLCL
–40
3t
CLCL
–45
145
83
3t
CLCL
–105
0
0
0
59
312
10
38
208
10
t
CLCL
–25
5t
CLCL
–105
10
3, 4
3
3
3
3
3
3
3
3, 4
3, 4
4
4
4
4
3, 4
Address valid to ALE low
RD pulse width
WR pulse width
RD low to valid data in
Data hold after RD
Data float after RD
ALE low to valid data in
Address to valid data in
ALE low to RD or WR low
Address valid to WR low or RD low
Data valid to WR transition
Data before WR
Data hold after WR
RD low to address float
RD or WR high to ALE high
43
400
400
23
275
275
t
CLCL
–40
6t
CLCL
–100
6t
CLCL
–100
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
252
148
5t
CLCL
–165
0
0
0
97
517
585
300
55
350
398
238
2t
CLCL
–70
8t
CLCL
–150
9t
CLCL
–165
3t
CLCL
+50
200
203
23
433
33
138
120
3
288
13
3t
CLCL
–50
4t
CLCL
–130
t
CLCL
–60
7t
CLCL
–150
t
CLCL
–50
0
0
0
43
123
23
103
t
CLCL
–40
t
CLCL
+40
5
5
5
5
High time
3
Low time
3
Rise time
3
Fall time
3
20
20
20
20
20
20
ns
ns
ns
ns
20
20
20
20
20
20
1.0
700
50
0
0.75
492
8
0
12t
CLCL
10t
CLCL
–133
2t
CLCL
–117
0
μ
s
ns
ns
ns
ns
700
492
10t
CLCL
–133
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