參數(shù)資料
型號(hào)： 85301AGL
英文描述： 2:1 DIFFERENTIAL-TO-LVPECL MULTIPLEXER
中文描述： 2:1差分至的LVPECL復(fù)用器
文件頁數(shù)： 9/19頁
文件大小： 301K
代理商： 85301AGL
85301AK
www.icst.com/products/hiperclocks.html
REV. A JANUARY 16, 2006
9
Integrated
Circuit
Systems, Inc.
ICS85301
2:1
D
IFFERENTIAL
-
TO
-LVPECL M
ULTIPLEXER
LVPECL C
LOCK
I
NPUT
I
NTERFACE
The PCLK /nPCLK accepts LVPECL, CML, SSTL and other
differential signals. Both V
and V
must meet the V
and V
input requirements.
Figures 2A to 2F
show inter-
face examples for the HiPerClockS PCLK/nPCLK input driven
by the most common driver types. The input interfaces sug-
gested here are examples only. If the driver is from another
vendor, use their termination recommendation. Please con-
sult with the vendor of the driver component to confirm the
driver termination requirements.
F
IGURE
2A.
H
I
P
ER
C
LOCK
S PCLK/nPCLK I
NPUT
D
RIVEN
BY
AN
O
PEN
C
OLLECTOR
CML D
RIVER
F
IGURE
2B.
H
I
P
ER
C
LOCK
S PCLK/nPCLK I
NPUT
D
RIVEN
BY
A
B
UILT
-I
N
P
ULLUP
CML D
RIVER
F
IGURE
2C. H
I
P
ER
C
LOCK
S PCLK/nPCLK I
NPUT
D
RIVEN
BY
A
3.3V LVPECL D
RIVER
F
IGURE
2F.
H
I
P
ER
C
LOCK
S PCLK/nPCLK I
NPUT
D
RIVEN
BY
A
3.3V LVDS D
RIVER
2.5V
Zo = 60 Ohm
SSTL
HiPerClockS
PCLK
nPCLK
R2
120
3.3V
R3
120
Zo = 60 Ohm
R1
120
R4
120
2.5V
F
IGURE
2E.
H
I
P
ER
C
LOCK
S PCLK/nPCLK I
NPUT
D
RIVEN
BY
AN
SSTL D
RIVER
HiPerClockS
PCLK/nPCLK
PCLK
nPCLK
3.3V
R2
50
R1
50
3.3V
Zo = 50 Ohm
CML
3.3V
Zo = 50 Ohm
3.3V
HiPerClockS
Input
PCLK
nPCLK
R2
84
R3
125
Zo = 50 Ohm
R4
125
R1
84
LVPECL
3.3V
3.3V
Zo = 50 Ohm
F
IGURE
2D.
H
I
P
ER
C
LOCK
S PCLK/nPCLK I
NPUT
D
RIVEN
BY
A
3.3V LVPECL D
RIVER
WITH
AC C
OUPLE
3.3V
3.3V
CML Built-In Pullup
R1
100
PCLK
nPCLK
HiPerClockS
PCLK/nPCLK
Zo = 50 Ohm
Zo = 50 Ohm
R2
50
Zo = 50 Ohm
C1
R1
50
C2
PCLK/nPCLK
R5
100 - 200
Zo = 50 Ohm
R6
100 - 200
PCLK
nPCLK
VBB
3.3V LVPECL
3.3V
3.3V
LVDS
3.3V
Zo = 50 Ohm
3.3V
PCLK
nPCLK
VBB
R2
1K
C2
R1
1K
R5
100
C1
PCLK/nPCLK
Zo = 50 Ohm
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