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參數(shù)資料
| 型號(hào)： | 83C166 |
| 廠商： | SIEMENS AG |
| 英文描述： | 16-Bit CMOS Single-Chip Microcontroller |
| 中文描述： | 16位CMOS單芯片微控制器 |
| 文件頁數(shù)： | 49/52頁 |
| 文件大?。?/td> | 541K |
| 代理商： | 83C166 |
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SAB 80C166/83C166
Semiconductor Group
48
Figure 14
CLKOUT and READY
Notes
1)
Cycle as programmed, including MCTC waitstates (Example shows 0 MCTC WS).
2)
The leading edge of the respective command depends on RW-delay.
3)
READY sampled HIGH at this sampling point generates a READY controlled waitstate,
READY sampled LOW at this sampling point terminates the currently running bus cycle.
4)
READY may be deactivated in response to the trailing (rising) edge of the corresponding command (RD or
WR).
5)
If the Asynchronous READY signal does not fulfill the indicated setup and hold times with respect to CLKOUT
(e.g. because CLKOUT is not enabled), it must fulfill t
37
in order to be safely synchronized. This is guaranteed,
if READY is removed in response to the command (see Note
4)
).
6)
Multiplexed bus modes have a MUX waitstate added after a bus cycle, and an additional MTTC waitstate may
be inserted here.
For a multiplexed bus with MTTC waitstate this delay is 2 CLKOUT cycles, for a demultiplexed bus without
MTTC waitstate this delay is zero.
7)
The next external bus cycle may start here.
CLKOUT
ALE
t
30
t
34
Sync
READY
t
35
t
36
t
35
t
36
Async
READY
t
58
t
59
t
58
t
59
waitstate
READY
MUX/Tristate
6)
t
32
t
33
t
29
Running cycle
1)
t
31
t
37
3)
3)
5)
Command
RD, WR
t
60
4)
see 6)
2)
7)
3)
3)
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