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參數(shù)資料
| 型號(hào)： | 83C166 |
| 廠商： | SIEMENS AG |
| 英文描述： | 16-Bit CMOS Single-Chip Microcontroller |
| 中文描述： | 16位CMOS單芯片微控制器 |
| 文件頁(yè)數(shù)： | 33/52頁(yè) |
| 文件大?。?/td> | 541K |
| 代理商： | 83C166 |
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SAB 80C166/83C166
Semiconductor Group
32
A/D Converter Characteristics
V
CC
= 5 V
±
10 %;
T
A
= 0 to +70 C
T
A
= -40 to +85 C
4.0 V
≤
V
AREF
≤
V
CC
+0.1 V;
V
SS
-0.1 V
≤
V
AGND
≤
V
SS
+0.2 V
V
SS
= 0 V
for SAB 83C166-5M, SAB 80C166-M
for SAB 83C166-5M-T3, SAB 80C166-M-T3
Notes
1)
V
AIN
may exceed
V
AGND
or
V
AREF
up to the absolute maximum ratings. However, the conversion result in these
cases will be X000
H
or X3FF
H
, respectively.
2)
During the sample time the input capacitance
C
I
can be charged/discharged by the external source. The
internal resistance of the analog source must allow the capacitors to reach their final voltage level within
t
S
.
After the end of the sample time
t
S
, changes of the analog input voltage have no effect on the conversion result.
The value for the sample clock is
t
SC
= TCL * 32.
3)
This parameter includes the sample time
t
S
, the time for determining the digital result and the time to load the
result register with the conversion result.
The value for the conversion clock is
t
CC
= TCL * 32.
4)
This parameter depends on the ADC control logic. It is not a real maximum value, but rather a fixum.
5)
TUE is tested at
V
AREF
= 5.0V,
V
AGND
= 0 V,
V
CC
= 4.8 V. It is guaranteed by design characterization for all
other voltages within the defined voltage range.
6)
During the conversion the ADC’s capacitance must be repeatedly charged or discharged. The internal
resistance of the reference voltage source must allow the capacitors to reach their respective voltage level
within
t
CC
. The maximum internal resistance results from the CPU clock period.
7)
Not 100% tested, guaranteed by design characterization.
Parameter
Symbol
Limit Values
Unit
Test Condition
min.
max.
V
AREF
2
t
SC
10
t
CC
+
t
S
+ 4TCL
±
2
t
CC
/ 250
- 0.25
t
S
/ 500
- 0.25
Analog input voltage range
V
AIN
SR
V
AGND
t
S
CC –
t
C
CC –
V
1)
Sample time
2) 4)
Conversion time
3) 4)
Total unadjusted error
TUE CC –
R
AREF
SR –
LSB
k
5)
Internal resistance of reference
voltage source
t
CC
in [ns]
6)
7)
Internal resistance of analog
source
R
ASRC
SR –
k
t
S
in [ns]
2)
7)
ADC input capacitance
C
AIN
CC –
50
pF
7)
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