參數(shù)資料
型號(hào)： 83C166
廠商： SIEMENS AG
英文描述： 16-Bit CMOS Single-Chip Microcontroller
中文描述： 16位CMOS單芯片微控制器
文件頁(yè)數(shù)： 15/52頁(yè)
文件大?。?/td> 541K
代理商： 83C166
SAB 80C166/83C166
Semiconductor Group
14
The SAB 80C166 also provides an excellent mechanism to identify and to process exceptions or
error conditions that arise during run-time, so-called ‘Hardware Traps’. Hardware traps cause
immediate non-maskable system reaction which is similar to a standard interrupt service (branching
to a dedicated vector table location). The occurrence of a hardware trap is additionally signified by
an individual bit in the trap flag register (TFR). Except when another higher prioritized trap service
is in progress, a hardware trap will interrupt any actual program execution. In turn, hardware trap
services can normally not be interrupted by standard or PEC interrupts.
The following table shows all of the possible exceptions or error conditions that can arise during run-
time:
Exception Condition
Trap
Flag
Trap
Vector
Vector
Location
Trap
Number
Trap
Priority
Reset Functions:
Hardware Reset
Software Reset
Watchdog Timer Overflow
RESET
RESET
RESET
0000
H
0000
H
0000
H
00
H
00
H
00
H
III
III
III
Class A Hardware Traps:
Non-Maskable Interrupt
Stack Overflow
Stack Underflow
NMI
STKOF
STKUF
NMITRAP
STOTRAP
STUTRAP
0008
H
0010
H
0018
H
02
H
04
H
06
H
II
II
II
Class B Hardware Traps:
Undefined Opcode
Protected Instruction
Fault
Illegal Word Operand
Access
Illegal Instruction Access
Illegal External Bus
Access
UNDOPC
PRTFLT
ILLOPA
ILLINA
ILLBUS
BTRAP
BTRAP
BTRAP
BTRAP
BTRAP
0028
H
0028
H
0028
H
0028
H
0028
H
0A
H
0A
H
0A
H
0A
H
0A
H
I
I
I
I
I
Reserved
[002C
H
–
003C
H
]
Any
[0000
H
–
01FC
H
]
in steps
of 04
H
[0B
H
– 0F
H
]
Software Traps
TRAP Instruction
Any
[00
H
– 7F
H
]
Current
CPU
Priority
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