參數(shù)資料
型號: 83C166
廠商: SIEMENS AG
英文描述: 16-Bit CMOS Single-Chip Microcontroller
中文描述: 16位CMOS單芯片微控制器
文件頁數(shù): 48/52頁
文件大?。?/td> 541K
代理商: 83C166
SAB 80C166/83C166
Semiconductor Group
47
AC Characteristics
(cont’d)
CLKOUT and READY
V
CC
= 5 V
±
10 %;
T
A
= 0 to +70 C
T
A
= -40 to +85 C
C
L
(for Port 0, Port 1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF
V
SS
= 0 V
for SAB 83C166-5M, SAB 80C166-M
for SAB 83C166-5M-T3, SAB 80C166-M-T3
Notes
1)
These timings are given for test purposes only, in order to assure recognition at a specific clock edge.
2)
Demultiplexed bus is the worst case. For multiplexed bus 2TCL are to be added to the maximum values. This
adds even more time for deactivating READY.
Parameter
Symbol
Max. CPU Clock
= 20 MHz
Variable CPU Clock
1/2TCL = 1 to 20 MHz
Unit
min.
max.
min.
max.
CLKOUT cycle time
t
29
t
30
t
31
t
32
t
33
t
34
CC
50
50
2TCL
2TCL
ns
CLKOUT high time
CC
20
TCL – 5
ns
CLKOUT low time
CC
15
TCL – 10
ns
CLKOUT rise time
CC
5
5
ns
CLKOUT fall time
CC
5
5
ns
CLKOUT rising edge to
ALE falling edge
CC
0 +
t
A
10 +
t
A
0 +
t
A
10 +
t
A
ns
Synchronous READY
setup time to CLKOUT
t
35
SR
10
10
ns
Synchronous READY
hold time after CLKOUT
t
36
SR
10
10
ns
Asynchronous READY
low time
t
37
SR
65
2TCL + 15
ns
Asynchronous READY
setup time
1)
t
58
SR
20
20
ns
Asynchronous READY
hold time
1)
t
59
SR
0
0
ns
Async. READY hold time
after RD, WR high
(Demultiplexed Bus)
2)
t
60
SR
0
0
+
2
t
A
+
t
F
2)
0
TCL - 25
+
2
t
A
+
t
F
2)
ns
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