參數(shù)資料
型號(hào)： 82C205
英文描述： Consumer IC
中文描述： 消費(fèi)性IC
文件頁(yè)數(shù)： 39/47頁(yè)
文件大?。?/td> 460K
代理商： 82C205
Advance Information
82C205
912-1000-024
Revision 1.0
Page 35
5.17. CLUT Access Control
7
6
5
4
3
2
1
0
Index B6h -B7h
Reserved
Default = 00h
5.18. ADC and PLL Control Registers
7
6
5
4
3
2
1
0
Index B8h C2h
Reserved
Default = 00h
Index C3h
VCLK1 Phase Offset (R/W)
Default = 09h
Reserved
Phase offset for VCLK1
Index C4h
MCLK PLL Control (R/W)
14.318 Mhz reference clock * N/M = MCLK frequency
Default = 02h
Divide MCLK
PLL output
frequency by 2
(If enabled,
the output of
the MCLK PLL
will be divided
by 2):
0: Disable
1: Enable
MCLK PLL M Factor (M[5:0])
Index C5h
MCLK PLL Control (R/W)
Default = 09h
Reserved
MCLK PLL N Factor (N[6:0])
Index C6h
VCLK2 PLL Control (R/W)
14.318 Mhz reference clock * N/M = VCLK2 frequency
Default = 02h
Divide VCLK2
PLL output
frequency by
2:
0: Disable
1: Enable
VCLK2 PLL M Factor (M[5:0])
Index C7h
VCLK2 PLL Control (R/W)
Default = 03h
VCLK2 PLL N Factor (N[6:0])
5.19. Power Management Registers
7
6
5
4
3
2
1
0
Index C8h
Power Enables for Panel Voltages (R/W)
Default = 00h
This power up/down sequencing is very important.
Improper sequencing can cause panel damage!
These signals default to zero at reset, i.e. inactive.
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
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