Advance Information
82C205
912-1000-024
Page 8
Revision 1.0
3.3. Signal Descriptions
3.3.1.
Terminology/Nomenclature Conventions
The "#" symbol at the end of a signal name indicates that the active, or asserted state occurs when the signal is at
a low voltage level. When "#" is not present after the signal name, the signal is asserted when at the high voltage
level.
The terms "assertion" and "negation" are used extensively. This is done to avoid confusion when working with a
mixture of "active low" and "active high" signals. The term "assert", or "assertion", indicates that a signal is active,
independent of whether that level is represented by a high or low voltage. The term "negate", or "negation",
indicates that a signal is inactive.
3.3.2.
CPU and System Interface
Signal Name
Pin
No.
Signal
Type
Signal Description
CPU_RD#
TEST_IN
205
I
CPU active low read strobe when TMS=0.
Test Input for Nand Tree and Tri-state tests when TMS=1
CPU_WR#
TSCAN_EN
204
I
CPU active low write strobe when TMS=0.
Reserved Input for tests when TMS=1
ALE+TMODE
203
I
CPU Address latch enable.
ChromaCast latches address from CPU address/data bus at negative edge of ALE.
When TMS=1, TMODE selects between NAND tree and tri-state testing (see Section
3.4, "Test Mode Signals").
CPUAD_[15:5]
CPUAD_[7:0]
190
-
199
I
I/O
CPU address/data bus bits [15:0]
Low Byte ([7:0]) is multiplexed data and the lower address byte.
Upper Byte (15:8) is upper address byte.
CPUINT +
TESTOUT
201
O
CPU active low interrupt when TMS=0.
Test Output for Nand Tree and Tri-state Tests when TMS=1
RESET#
207
I
ChromaCast System Reset (active low).
The minimum RESET time is 1ms, i.e. the RESET signal should stays active for at
least 1ms after power is stabilized.
REFCK
206
I
Reference Clock. 14.318 MHz reference clock driven externally.
This same 14MHz clock must be used to drive the external microcontroller.
PSEN#
202
I
Program strobe enable.
Active low signal indicates that the CPU needs to fetch a progarm instruction.
TMS
208
I
Test Mode Select – Sets test mode at power-up (see Secton 3.4, "Test Mode
Signals").
TMS=0: Normal operation
TMS=1: Test mode