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參數(shù)資料
| 型號： | 82C205 |
| 英文描述： | Consumer IC |
| 中文描述： | 消費性IC |
| 文件頁數(shù)： | 21/47頁 |
| 文件大?。?/td> | 460K |
| 代理商： | 82C205 |
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Advance Information
82C205
912-1000-024
Revision 1.0
Page 17
Bit[5]
Bit[4]
Bit[3]
Bits[2:1]
Bit[0]
Red
Green
Blue
CLUT contents
Overlay
α
Figure 3.
A global alpha is defined for the entire table, and each entry is tagged with an alpha-blend flag. Inverted video,
transparent and blinking attributes are also supported in this mode.
Using the alpha blend value, the OSD graphics can be composited with the video stream controlled by a blend
factor in order to create a translucent effect. Pixels in the defined rectangular OSD region that the programmer
wishes to be “blank” graphics, i.e. the underlying video is clearly visible, can attach the “transparent” attribute to
the OSD pixel. The formula used to control alpha blending is as follows:
Output = Video * (1-
α
) + OSD * (
α
)
Attributes further expand the OSD effects, with an invert attribute (which inverts the video data) and a blink
attribute, which performs a hardware controlled blink using a programmable blink rate.
4.9. Dithering
Some flat panels do not provide a 24-bit “true color” interface, so the challenge is to achieve the effect of true color
when the panel itself supports less than a full color display. OPTi uses an advanced dithering technique which
delivers a true color effect on all display types.
4.10. Versatile Panel Support
The 82C205 is configurable to support a wide range of active matrix displays with resolutions of 640 x 480, 800 x
600, 1024 x 768, and 1280 x 1024 pixels. TFT displays with 9-, 12-, 18-, and 24-bits per pixel are supported.
82C205 also supports multiple pixels per clock and provides a 36-bit interface for panel support.
The synchronization signals to the flat panel are controlled by a fully programmable display CRTC. Positive and
negative polarity syncs are supported. In addition to the horizontal and vertical syncs, and the pixel clock for the
panel, a data ready (DE) signal is also provided for TFT displays
4.11. Clock Generation
82C205 contains two internal PLLs that are used to generate the clocks necessary for operation. In addition to
these two clocks, which control the video processing unit and the memory subsystem, the 14.318 Mhz reference
clock is also used internally. This 14.319Mhz same as the system clock for the micro-controller interface.
§
PLL2 (MCK) uses the 14.318 MHz reference clock to generate the clock for the memory controller. This clock
frequency should match the speed of the DRAM. For SDRAM, a 100 MHz clock is recommended.
§
PLL3 (VCLK2) uses the 14.318 MHz reference clock to generate the display clock for the video processing
unit. This is also the clock that will be used to drive the panel and its frequency is closely linked to the panel
specifications.
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